Publications

  • “Kill the program counter: Reconstructing program behavior at the last level cache,”Jinchun Kim, Elvira Teran, Paul V. Gratz, Daniel Jimenez, Seth Pugsley, and Chris Wilkerson.  In the 22nd International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), April 2017. (Accepted for Publication),
  • “Path Confidence based Lookahead Prefetching”, J. Kim , S. Pugsley, P. V. Gratz, A. Reddy, C. Wilkerson, Z. Chishti, The 49th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), Oct. 2016.  (Nominated for Best Paper) pdfbibtex.
  • “SDPR: Improving Latency and Bandwidth in On-Chip Interconnect through Simultaneous Dual-Path Routing”, Y. S. Yang, H. Deshpande, G. Choi, P. V. Gratz, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, (Accepted for Publication, in pre-press.)
  • “Resource Sharing Centric Dynamic Voltage and Frequency Scaling for CMP Cores, Uncore, and Memory”, J-Y Won, P. V. Gratz, S. Shakkottai, and J. Hu. 2016. ACM Transactions on Design Automation of Electronic Systems (TODAES), 21, 4, Article 69 (May 2016)
  • “Energy-Efficient Implementations of GF(p)and GF(2^m)Elliptic Curve Cryptography”, Andrew D. Targhetta, Donald E. Owen Jr., Francis L. Israel and Paul V. Gratz, The 33rd IEEE International Conference on Computer Design (ICCD), Oct. 2015. (Nominated for Best Paper)
  • “Clotho: Proactive Wearout Deceleration in Chip-Multiprocessor Interconnects”, Arseniy Vitkovskiy, Paul V. Gratz and Vassos Soteriou, The 33rd IEEE International Conference on Computer Design (ICCD), Oct. 2015.
  • “Dynamic Memory Pressure Aware Ballooning”, J. Kim, V. Fedorov, P. V. Gratz, A.L.N. Reddy, The International Symposium on Memory Systems (MEMSYS’15), Oct. 2015.
  • “Shared Last-Level Caches and The Case for Longer Timeslices”, V. Fedorov, A.L.N. Reddy, P. V. Gratz, The International Symposium on Memory Systems (MEMSYS’15), Oct. 2015.
  • “Use It or Lose It: Proactive, Deterministic Longevity in Future Chip Multiprocessors”, Hyungjun Kim, Siva Bhanu Krishna Boga, Arseniy Vitkovskiy, Stavros Hadjitheophanous, Paul V. Gratz, Vassos Soteriou, and Maria K. Michael, ACM Transactions on Design Automation of Electronic Systems (TODAES) 20, 4, Article 65 (September 2015)
  • “Having Your Cake and Eating It Too: Energy Savings without Performance Loss Through Resource Sharing Driven Power Management,” J.-Y. Won, P.V. Gratz, S. Shakkottai and J. Hu, ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED), July 2015.
  • “A Control-Theoretic Approach for Energy Efficient CPU-GPU Subsystem in Mobile Platforms”, D. Kadjo, R. Ayoub, M. Kishinevsky, and P. Gratz. The 52th ACM/EDAC/IEEE The Design Automation Conference (DAC), June 2015. (Nominated for Best Paper)
  • “A Bandwidth Efficient On-Chip Interconnects Design for GPGPUs”, H. Jang, J. Kim, P. Gratz, K. Yum, E. Kim. The 52th ACM/EDAC/IEEE The Design Automation Conference (DAC), June 2015.
  • “B-Fetch: Branch Prediction Directed Prefetching for Chip-Multiprocessors”, D. Kadjo, J. Kim, P. Sharma, R. Panda, P. V. Gratz, D. A. Jim ́enez, The 47th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), Dec. 2014.   (Nominated for Best Paper)  pdfbibtex.
  • “Towards Platform Level Power Management in Mobile Systems”, D. Kadjo. Ogras, R. Ayoub, M. Kishinevsky, P. V. Gratz, the 27th IEEE International SOC Conference (SOCC), Sept. 2014.
  • “STORM: A Simple Traffic-Optimized Router Microarchitecture for Networks-on-Chip”, S. Rasheed, P. Gratz, S. Shakkottai, J. Hu,  The 8th International Symposium on Networks-on-Chip (NOCS), Sept. 2014. (Poster and Abstract)
  • “WaveSync: Low-Latency Source Synchronous Bypass Network-On-Chip Architecture”, Y. Yang, R. Kumar, G. Choi, P. V. Gratz, ACM Transactions on Design Automation of Electronic Systems, 19, 4, Article 34 (August 2014)
  • “ILP and TLP in Shared Memory Applications: A Limit Study”, E. Fatehi, P. V. Gratz, The 23rd International Conference on Parallel Architectures and Compilation Techniques (PACT), Aug. 2014.  pdfbibtex.
  • “LumiNOC: A Power-Efficient, High-Performance, Photonic Network-on-Chip”, C. Li, M. Browning, P. V. Gratz, S. Palermo, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.33, no.6, pp.826,838, June 2014. pdfbibtex.
  • “The Design Space of Ultra-low Energy Asymmetric Cryptography”, A. D. Targhetta, D. E. Owen Jr., P. V. Gratz, The 2014 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), Mar. 2014. pdfbibtex.
  • “Up By Their Bootstraps: Online Learning in Artificial Neural Networks for CMP Uncore Power Management”, J. Won, X. Chen, P. V. Gratz, J. Hu, and V. Soteriou, The 20th IEEE International Symposium on High Performance Computer Architecture (HPCA), Feb. 2014. pdfbibtex.
  • “ARI: Adaptive LLC-Memory Traffic Management”, V. Fedorov, S. Qiu, R.A.L.Narasimha, P. V. Gratz, The ACM Transactions on Architecture and Code Optimizations  (TACO), vol.10, no.4, Jan. 2014. (also co-published in HiPEAC’14). pdfbibtex.
  • “Use It Or Lose It: Wear-out and Lifetime in Future Chip Multiprocessors”, H. Kim, A. Vitkovskiy, P. Gratz, and V. Soteriou, The 46th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), Dec. 2013. pdfbibtex. Selected for “HiPEAC Paper Award” by the HiPEAC Network of Excellence.
  • “In-network Monitoring and Control Policy for DVFS of CMP Networks-on-Chip and

    Last Level Caches”, X. Chen, Z. Xu, H. Kim, P.V. Gratz and J. Hu, M. Kishinevsky and U. Ogras, ACM Transactions on Design Automation of Electronic Systems (TODAES),

    vol.18, no.4, art.47, Oct. 2013. pdfbibtex.

  • “Power Gating with Block Migration in Chip-Multiprocessor Last-Level Caches”, D. Kadjo, H. Kim, P. Gratz, J. Hu and R. Ayoub, The 31st IEEE International Conference on Computer Design (ICCD), Oct. 2013. pdfbibtex.
  • “Stochastic Pre-Classification for Software Defined Firewalls”, P. Ghoshal, C. J. Casey, P. V. Gratz, A. Sprintson. The 22nd International Conference on Computer Communications and Networks (ICCCN), July 2013. pdfbibtex.
  • “Dynamic Voltage and Frequency Scaling for Shared Resources in Multicore Processor Designs”, X. Chen, Z. Xu, H. Kim, P. Gratz, J. Hu, M. Kishinevsky, U. Ogras and R. Ayoub. The 50th ACM/EDAC/IEEE The Design Automation Conference (DAC), June 2013. pdfbibtex.
  • Invited Talk: “LumiNOC: A Low-Latency, High Bandwidth per Watt Photonic Network-on-Chip”, C. Li, M. Browning, P. V. Gratz and S. Palermo. The 15th IEEE/ACM System Level Interconnect Prediction Workshop (SLIP), June 2013. (Tech Reportpresentation)
  • “Bidirectional Interconnect Design for Low Latency High Bandwidth NoC”, R. Kumar, H. Deshpande, G. Choi, A. Sprintson, P. Gratz , 2013 International Conference on IC Design and Technology, May 2013.  pdfbibtex.
  • “GCA:Global Congestion Awareness for Load Balance in Networks-on-Chip”, M. Ramakrishna, P. V. Gratz and A. Sprintson. The Seventh ACM/IEEE International Symposium on Networks-on-Chip (NOCS), April 2013. pdfbibtex.
  • “LumiNOC: A Power-Efficient, High-Performance, Photonic Network-on-Chip for Future Parallel Architectures”, C. Li, M. Browning, P. V. Gratz and S. Palermo. The Seventh ACM/IEEE International Symposium on Networks-on-Chip (NOCS), April 2013. (poster and presentation) (Tech Report).
  • “NOCS Special Section: Spatial Locality Speculation to Reduce Energy in Chip-Multiprocessor Networks-on-Chip”, H. Kim, B. Grot, P. V. Gratz, D. Jiminez,  IEEE Transactions on Computers, vol.PP, no.99, pp.1 (to appear)
  • “B-Fetch: Branch Prediction Directed Prefetching for In-Order Processors,” Reena Panda , Paul V. Gratz , and Daniel A. Jimenez, IEEE Computer Architecture Letters, vol.11, no.2, pp.41,44, July-Dec. 2012. Selected for “Best Papers from IEEE Computer Architecture Letters”.  pdfbibtex.
  • “WaveSync: Low-Latency Source Synchronous Bypass Network-On-Chip Architecture”, Y. Yang, R. Kumar, G. Choi and P. V. Gratz, The 30th IEEE International Conference on Computer Design (ICCD), Oct. 2012. pdfbibtex.
  • “LumiNOC: A Power-Efficient, High-Performance, Photonic Network-on-Chip for Future Parallel Architectures”, C. Li, M. Browning, P. V. Gratz and S. Palermo. The 21st International Conference on Parallel Architectures and Compilation Techniques (PACT), Sept. 2012. (Poster and Abstractbibtex.
  • “Energy-efficient Optical Broadcast for Nanophotonic Networks-on-Chip”, C. Li, M. Browning, P. V. Gratz and S. Palermo. The 2012 IEEE Optical Interconnects Conference (OIC), May 2012.  pdfbibtex.
  • “In-Network Monitoring and Control Policy for DVFS of CMP Networks-On-Chip and Last Level Caches”, Xi Chen, Zheng Xu, Hyungjun Kim, Paul Gratz, Jiang Hu, Michael Kishinevsky and Umit Ogras. The Sixth ACM/IEEE International Symposium on Networks-on-Chip (NOCS), May 2012. (Nominated for Best Paper)  pdfbibtex.
  • “Exploiting Path Diversity for Low-Latency and High-Bandwidth with the Dual-path NoC Router,” Y. S. Yang, H. Deshpande, G.  Choi and P. V. Gratz. The 2012 IEEE International Symposium on Circuits and Systems (ISCAS), May 2012.  pdfbibtex.
  • “An Energy Efficient Datapath for Asymmetric Cryptography,” Andrew D. Targhetta and Paul V. Gratz, 3rd Workshop on Energy Efficient Design (WEED 2011), June 2011.  pdfbibtex.
  • “Asynchronous Bypass Channels for Multi-synchronous NoCs: A Router Microarchitecture, Topology and Routing Algorithm,” Tushar N. K. Jain, Mukund Ramakrishna, Paul V. Gratz, Alex Sprintson and Gwan Choi. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.30, no.11, pp.1663-1676, Nov. 2011. pdfbibtex.
  • “Reducing Network-on-Chip Energy Consumption Through Spatial Locality Speculation,” Hyungjun Kim, Pritha Ghoshal, Boris Grot, Paul V. Gratz and Daniel A. Jimenez. The Fifth ACM/IEEE International Symposium on Networks-on-Chip (NOCS), May 2011. pdfbibtex
  • “AcENoCs: A Configurable HW/SW Platform for FPGA Accelerated NoC Emulation,” V. Pai, S. Lotlikar, and P. V. Gratz. The 24th IEEE International Conference on VLSI Design (VLSID), Jan. 2011. pdfbibtex
  • “Leveraging Unused Cache Block Words to Reduce Power in CMP Interconnect,” Hyungjun Kim, Paul Gratz, IEEE Computer Architecture Letters, 9(1), pp.33-36, January 2010. pdfbibtex.
  • “Asynchronous Bypass Channel Routers: Improving Performance for DVFS and GALS NoCs,” Tushar Jain, Paul Gratz, Alex Sprintson, and Gwan Choi, The 4th ACM/IEEE International Symposium on Networks-on-Chip, May 2010. pdf,bibtex.
  • “Ocin_sim – a DVFS aware simulator for NoC based platforms”, Subodh Prabhu, Boris Grot, Paul V. Gratz and Jiang Hu.The 1st Workshop on SoC Archtecture, Accelerators and Workloads (SAW-1), January 2010. pdfbibtexwebsite.
  • “Realistic Workload Characterization and Analysis for Networks-on-Chip Design”, Paul V. Gratz and Stephen W. Keckler. The 4th Workshop on Chip Multiprocessor Memory Systems and Interconnects (CMP-MSI), January 2010. pdfbibtex.
  • “Running PARSEC 2.1 on M5”, Mark Gebhart, Joel Hestness, Ehsan Fatehi, Paul Gratz, Stephen W. Keckler; The University of Texas at Austin, Department of Computer Science. Technical Report #TR-09-32. October 27, 2009. pdf,bibtexwebsite
  • “Asynchronous Bypass Channel Routers,” Tushar Jain, Paul Gratz, Alex Sprintson, and Gwan Choi, Technical Report:TAMU-ECE-2009-05, August 24, 2009, bibtex.
  • “Evaluation of the TRIPS Computer System,” M. Gebhart, B. A. Maher, K. E. Coons, J. Diamond, P. Gratz, M. Marino, N. Ranganathan, B. Robatmili, A. Smith, J. Burrill, S. W. Keckler, D. Burger, K. S. McKinley. The 14th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), March 2009(Received best paper award). pdfbibtex.
  • “Regional Congestion Awareness for Load Balance in Networks-on-Chip,” P. Gratz, B. Grot, and S.W. Keckler. The 14th IEEE International Symposium on High-Performance Computer Architecture (HPCA), February 2008. pdfbibtex.
  • “On-Chip Interconnection Networks of the TRIPS Chip,” P. Gratz, C. Kim, K. Sankaralingam, H. Hanson, P. Shivakumar, S.W. Keckler, and D.C. Burger. IEEE Micro, 27(5), pp. 41-50, September/October 2007. pdfbibtex.
  • “TRIPS: A Distributed Explicit Data Graph Execution (EDGE) Microprocessor,” M.S. Govindan, K. Sankaralingam, R. Nagarajan, R. McDonald, R. Desikan, S. Drolia, P. Gratz, D. Gulati, H. Hanson, C.K. Kim, H. Liu, N. Ranganathan, S. Sethumadhavan, S. Sharif, P. Shivakumar, S.W. Keckler, and D. Burger, HotChips 19, August 2007.
  • “Implementation and Evaluation of a Dynamically Routed Processor Operand Network,” P. Gratz, K. Sankaralingam, H. Hanson, P. Shivakumar, R. McDonald, S.W. Keckler, and D.C. Burger. The First IEEE International Symposium on Networks-on-Chips (NOCS), pp 7 – 17, May, 2007. pdfbibtex.
  • “Distributed Microarchitectural Protocols in the TRIPS Prototype Processor,” K. Sankaralingam, R. Nagarajan, R. McDonald, R. Desikan, S. Drolia, M.S. Govindan, P. Gratz, D. Gulati, H. Hanson, C. Kim, H. Liu, N. Ranganathan, S. Sethumadhavan, S. Sharif, P.K. Shivakumar, S. W. Keckler, D.C. Burger. The 36th IEEE/ACM International Symposium on Microarchitecture (MICRO), pp. 480 – 491, December 2006. pdfbibtex.
  • “Implementation and Evaluation of On-Chip Network Architectures,” P. Gratz, C. Kim, R. McDonald, S.W. Keckler, and D.C. Burger. 2006 IEEE International Conference on Computer Design (ICCD), pp 477 – 484, October, 2006. pdfbibtex.
  • “Scaling to the End of Silicon with EDGE Architectures,” D.C. Burger, S.W. Keckler, K.S. McKinley, et al. IEEE Computer, 37 (7), pp. 44-55, July, 2004.pdf.