Talks

Selected Invited Presentations

  • Simulation and Macromodeling of DC-DC Converters, Texas Analog Center of Excellence (TxAcE), University of Texas, Dallas, July 2015
  • Advanced Design Automation Methodologies for Next-Generation Power Delivery Networks, Tutorial at IEEE/ACM Design Automation Conference, San Francisco, CA, June 2015
    Organizer and Presenter with Zhuo Feng (Michigan Technological Univ.), Cheng Zhuo (Intel) and Karthikeyan Ramamurthi (Intel)
  • Biophysically based Computational Simulation of Oscillatory Activities of the BrainPierre and Marie Curie University (UPMC), Paris, France, March 2015
  • Computational Modeling and Simulation of Synchronized Firing Behaviors of the Brain, Invited talk at Design, Automation and Test in Europe Conference (DATE), March 2015
  • Holistic Design of IC Power Delivery: Design Tradeoffs and System Optimization, Shanghai Jiao Tong University, Shanghai, China, July 2014
  • Biophysically based Computational Simulation of Oscillatory Activities of the Brains, East China Normal University, Shanghai, China, July 2014
  • The Theory and Practice of Stability-Ensuring Design of IC Power Delivery with Distributed Voltage Regulators, Xi’an Jiaotong University, Xi’an, China, July 2014
  • Analysis of Oscillatory Behaviors of the Brain, DAC Workshop- They are all Networks! Analysis and Optimization for Electronics, Water, Electricity, Bio, IEEE/ACM Design Automation Conference (DAC), Austin, Texas, June 2013
  • Hierarchical Model Checking for Practical Analog/Mixed-Signal Design Verification, Freescale Semiconductors SRC Verification E-Forum, March 2013
  • Design Analysis of IC Power Delivery, ICCAD-2012 Special Session: Power Grid Simulation and Verification for Billion-Transistor VLSI Designs, IEEE/ACM Intl. Conf. on CAD (ICCAD), San Jose, California, November 2012
  • System Design and Analysis of IC Power Delivery, Fudan University, Shanghai, China and Institute of Microelectronics, Chinese Academy of Sciences, Beijing, China, August, 2012
  • Design and Analysis of IC Power Delivery with On-Chip Voltage Regulation
    International Conference on IC Design and Technology, Austin, Texas, May 2012
  • Circuit/System Co-Optimization of IC Power Delivery, Advanced Micro Devices, Austin, Texas, May 2012.
  • System-Level Modeling and Design of IC Power Delivery, Freescale Semiconductors, Austin, Texas, May 2012.
  • Property Checking and Design Assurance for Analog Circuits and Networks, Strategic CAD Lab, Intel Corporation, Hillsboro, OR, December 2011.
  • Leveraging GPU Computing for VLSI CAD and Beyond
    CANDE Workshop, San Jose, California, November 2011.
  • Design and Analysis of Power Delivery Networks with Voltage Regulation and Conversion, Intel Corporation, Hillsboro, OR, June 2011.
  • DAC Parallel EDA Panel, IEEE/ACM Design Automation Conference, San Diego, CA, June 2011.
  • Exploiting Parallelism for CAD: Algorithm Design and Implementation Strategies, DAC PAPA Workshop, San Diego, CA, June 2011.
  • From Integrated Circuit Design to Brain Modeling: Coping with System Complexity by Leveraging Application-Specific Parallel Computing, Ming Hsieh Department of Electrical Engineering, University of Southern California, Los Angeles, California, March 2011.
  • In-Situ Jitter Test and Diagnosis, IBM T. J. Watson Research Center, E-Seminar, NY, December 2010.
  • Analog Verification: Challenges and Perspectives, Intel Analog and Mixed-Signal CAD Workshop, Intel Corporation, Hillsboro, OR, July 2010.
  • Parallel Circuit Simulation: Algorithms and Runtime Optimization, SRC/Texas Analog Center of Excellence (University of Texas, Dallas), June 2010.
  • CAD Techniques for Large-Scale Circuit Simulation and Design Verification, Texas Instruments, February 2010.
  • Design and Verification of Power Delivery Networks, IBM Austin Research Laboratories, January 2010.
  • SRAM Dynamic Noise Margins: Concepts and Analysis, Circuit and Multi-Domain Simulation Workshop (CMS), November, 2009.
  • Parallel VLSI CAD: Exploring Parallelisms on Multi-core and Graphics Processors, IBM T. J. Watson Research Center, May 2009.
  • Parallel Preconditioned Harmonic Balance for Analog Circuit Analysis (invited presentation), SIAM Conference on Computational Science and Engineering, March 2009.
  • Parallel Transient Simulation on Multicore Shared-Memory Machines, IEEE CEDA (Council on Electronic Design Automation) Distinguished Speaker Seminar, Nov. 2008.
  • Parallel Circuit Simulation on Multi-core and GPU Platforms, Intel Strategic CAD Lab, Hillsboro, OR, November 2008.
  • Novel CAD Techniques for Analyzing SRAM Dynamic Stability and Large Power Grids, Advanced Micro Devices (AMD), Sunnyvale, CA, November 2008.
  • CAD for Analog: Variability, Modeling and Optimization, Cadence Design Systems, Pittsburgh, PA, April 2008.
  • Model Order Reduction of Parameterized Multi-Port Passive Networks for On-Chip Interconnect Design, Department of Mathematics, University of Texas, Arlington, April 2008.
  • Techniques for Parallel Circuit Simulation and SRAM Dynamic Stability Analysis, IBM Austin Research Lab, Austin, TX, January 2008.
  • Modeling and Analysis of Non-Tree Clock Distribution, Cadence Design Systems, San Jose, CA, November 2007.
  • Recent Results in RF Simulation and Macromodeling, Texas Instruments, Dallas, TX, July 2007.
  • Efficient Analog Circuit Analysis Using Hierarchically Preconditioned Harmonic Balance, Magma Design Automation, Austin TX, January 2007.
  • Coping with Complexity: Interconnect Variation Analysis and Simulation of Large Analog and Clock Networks, Freescale Semiconductor, Austin TX, November 2006.
  • Modeling and Analysis of Circuit Performance under Environmental and Process Variations, Intel Corporation, Austin TX, May 2006.
  • Analyzing Circuit Performance under Process, Temperature and Supply Variations, IBM Austin Research Lab, Austin, TX, March 2006.
  • Efficient Circuit Delay Analysis Considering Process, Temperature and Supply Variations, Mentor Graphics Corporation, Wilsonville, OR, March 2006.
  • Fast Circuit Performance Evaluation in the Presence of Process, Temperature and Supply Variations, Synopsys, Inc., Mountain View, CA, Feb 2006.
  • Full-Chip Thermal Modeling and Analysis, Intel Corporation, Santa Clara, CA, April 2005.
  • Hierarchical Approaches in Circuit Simulation, Presented at Shanghai Jiao Tong University, Fudan University, Xi’an Jiaotong University, China, Dec 2004 – Jan. 2005.
  • Nonlinear Reduced-Order Modeling for Analog and RF: Challenges and Opportunities, Department of Electrical and Engineering, University of Illinois at Urbana-Champaign, March 2004.
  • Nonlinear Reduced-Order Modeling for Analog and RF: Challenges and Opportunities, Department of Electrical Engineering, Yale University, March 2004.