Publications

  • “B-Fetch: Branch Prediction Directed Prefetching for Chip-Multiprocessors”, D. Kadjo, J. Kim, P. Sharma, R. Panda, P. V. Gratz, D. A. Jim ́enez, The 47th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), Dec. 2014.  (Accepted for publication)
  • “Towards Platform Level Power Management in Mobile Systems”, D. Kadjo. Ogras, R. Ayoub, M. Kishinevsky, P. V. Gratz, the 27th IEEE International SOC Conference (SOCC), Sept. 2014.  (Accepted for publication)
  • “WaveSync: Low-Latency Source Synchronous Bypass Network-On-Chip Architecture”, Y. Yang, R. Kumar, G. Choi, P. V. Gratz, ACM Transactions on Design Automation of Electronic Systems, (Accepted for publication)
  • “ILP and TLP in Shared Memory Applications: A Limit Study”, E. Fatehi1 , P. V. Gratz, The 23rd International Conference on Parallel Architectures and Compilation Techniques (PACT), Aug. 2014.
  • “LumiNOC: A Power-Efficient, High-Performance, Photonic Network-on-Chip”, C. Li, M. Browning, P. V. Gratz, S. Palermo, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, (Accepted for publication)
  • “The Design Space of Ultra-low Energy Asymmetric Cryptography”, A. D. Targhetta, D. E. Owen Jr., P. V. Gratz, The 2014 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), Mar. 2014.
  • “Up By Their Bootstraps: Online Learning in Artificial Neural Networks for CMP Uncore Power Management”, Jae-Yeon Won, Xi Chen, Paul V. Gratz, Jiang Hu, and Vassos Soteriou, The 20th IEEE International Symposium on High Performance Computer Architecture (HPCA), Feb. 2014.
  • “Use It Or Lose It: Wear-out and Lifetime in Future Chip Multiprocessors”, H. Kim, A. Vitkovskiy, P. Gratz, and V. Soteriou, The 46th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), Dec. 2013.
  • “Power Gating with Block Migration in Chip-Multiprocessor Last-Level Caches”, D. Kadjo, H. Kim, P. Gratz, J. Hu and R. Ayoub, The 31st IEEE International Conference on Computer Design (ICCD), Oct. 2013. pdfbibtex.
  • “Stochastic Pre-Classification for Software Defined Firewalls”, P. Ghoshal, C. J. Casey, P. V. Gratz, A. Sprintson. The 22nd International Conference on Computer Communications and Networks (ICCCN), July 2013. pdfbibtex.
  • “Dynamic Voltage and Frequency Scaling for Shared Resources in Multicore Processor Designs”, X. Chen, Z. Xu, H. Kim, P. Gratz, J. Hu, M. Kishinevsky, U. Ogras and R. Ayoub. The 50th ACM/EDAC/IEEE The Design Automation Conference (DAC), June 2013. pdfbibtex.
  • Invited Talk: “LumiNOC: A Low-Latency, High Bandwidth per Watt Photonic Network-on-Chip”, C. Li, M. Browning, P. V. Gratz and S. Palermo. The 15th IEEE/ACM System Level Interconnect Prediction Workshop (SLIP), June 2013. pdfpresentation
  • “Bidirectional Interconnect Design for Low Latency High Bandwidth NoC”, R. Kumar, H. Deshpande, G. Choi, A. Sprintson, P. Gratz , 2013 International Conference on IC Design and Technology, May 2013.  pdfbibtex.
  • “GCA:Global Congestion Awareness for Load Balance in Networks-on-Chip”, M. Ramakrishna, P. V. Gratz and A. Sprintson. The Seventh ACM/IEEE International Symposium on Networks-on-Chip (NOCS), April 2013. pdfbibtex.
  • “LumiNOC: A Power-Efficient, High-Performance, Photonic Network-on-Chip for Future Parallel Architectures”, C. Li, M. Browning, P. V. Gratz and S. Palermo. The Seventh ACM/IEEE International Symposium on Networks-on-Chip (NOCS), April 2013. (poster and presentation) pdf.
  • “NOCS Special Section: Spatial Locality Speculation to Reduce Energy in Chip-Multiprocessor Networks-on-Chip”, H. Kim, B. Grot, P. V. Gratz, D. Jiminez,  IEEE Transactions on Computers, vol.PP, no.99, pp.1 (to appear)
  • “B-Fetch: Branch Prediction Directed Prefetching for In-Order Processors,” Reena Panda , Paul V. Gratz , and Daniel A. Jimenez, IEEE Computer Architecture Letters, vol.11, no.2, pp.41,44, July-Dec. 2012. Selected for “Best Papers from IEEE Computer Architecture Letters”.  pdfbibtex.
  • “WaveSync: Low-Latency Source Synchronous Bypass Network-On-Chip Architecture”, Y. Yang, R. Kumar, G. Choi and P. V. Gratz, The 30th IEEE International Conference on Computer Design (ICCD), Oct. 2012. pdfbibtex.
  • “LumiNOC: A Power-Efficient, High-Performance, Photonic Network-on-Chip for Future Parallel Architectures”, C. Li, M. Browning, P. V. Gratz and S. Palermo. The 21st International Conference on Parallel Architectures and Compilation Techniques (PACT), Sept. 2012. (Poster and Abstractbibtex.
  • “Energy-efficient Optical Broadcast for Nanophotonic Networks-on-Chip”, C. Li, M. Browning, P. V. Gratz and S. Palermo. The 2012 IEEE Optical Interconnects Conference (OIC), May 2012.  pdfbibtex.
  • “In-Network Monitoring and Control Policy for DVFS of CMP Networks-On-Chip and Last Level Caches”, Xi Chen, Zheng Xu, Hyungjun Kim, Paul Gratz, Jiang Hu, Michael Kishinevsky and Umit Ogras. The Sixth ACM/IEEE International Symposium on Networks-on-Chip (NOCS), May 2012. (Nominated for Best Paper)  pdfbibtex.
  • “Exploiting Path Diversity for Low-Latency and High-Bandwidth with the Dual-path NoC Router,” Y. S. Yang, H. Deshpande, G.  Choi and P. V. Gratz. The 2012 IEEE International Symposium on Circuits and Systems (ISCAS), May 2012.  pdfbibtex.
  • “An Energy Efficient Datapath for Asymmetric Cryptography,” Andrew D. Targhetta and Paul V. Gratz, 3rd Workshop on Energy Efficient Design (WEED 2011), June 2011.  pdfbibtex.
  • “Asynchronous Bypass Channels for Multi-synchronous NoCs: A Router Microarchitecture, Topology and Routing Algorithm,” Tushar N. K. Jain, Mukund Ramakrishna, Paul V. Gratz, Alex Sprintson and Gwan Choi. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.30, no.11, pp.1663-1676, Nov. 2011. pdfbibtex.
  • “Reducing Network-on-Chip Energy Consumption Through Spatial Locality Speculation,” Hyungjun Kim, Pritha Ghoshal, Boris Grot, Paul V. Gratz and Daniel A. Jimenez. The Fifth ACM/IEEE International Symposium on Networks-on-Chip (NOCS), May 2011. pdfbibtex
  • “AcENoCs: A Configurable HW/SW Platform for FPGA Accelerated NoC Emulation,” V. Pai, S. Lotlikar, and P. V. Gratz. The 24th IEEE International Conference on VLSI Design (VLSID), Jan. 2011. pdfbibtex
  • “Leveraging Unused Cache Block Words to Reduce Power in CMP Interconnect,” Hyungjun Kim, Paul Gratz, IEEE Computer Architecture Letters, 9(1), pp.33-36, January 2010. pdfbibtex.
  • “Asynchronous Bypass Channel Routers: Improving Performance for DVFS and GALS NoCs,” Tushar Jain, Paul Gratz, Alex Sprintson, and Gwan Choi, The 4th ACM/IEEE International Symposium on Networks-on-Chip, May 2010. pdf,bibtex.
  • “Ocin_sim – a DVFS aware simulator for NoC based platforms”, Subodh Prabhu, Boris Grot, Paul V. Gratz and Jiang Hu.The 1st Workshop on SoC Archtecture, Accelerators and Workloads (SAW-1), January 2010. pdfbibtexwebsite.
  • “Realistic Workload Characterization and Analysis for Networks-on-Chip Design”, Paul V. Gratz and Stephen W. Keckler. The 4th Workshop on Chip Multiprocessor Memory Systems and Interconnects (CMP-MSI), January 2010. pdfbibtex.
  • “Running PARSEC 2.1 on M5”, Mark Gebhart, Joel Hestness, Ehsan Fatehi, Paul Gratz, Stephen W. Keckler; The University of Texas at Austin, Department of Computer Science. Technical Report #TR-09-32. October 27, 2009. pdf,bibtexwebsite
  • “Asynchronous Bypass Channel Routers,” Tushar Jain, Paul Gratz, Alex Sprintson, and Gwan Choi, Technical Report:TAMU-ECE-2009-05, August 24, 2009, bibtex.