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Fishbowl Seminar: A Holistic Approach Towards Intelligent Hotspot Prevention in Network-on-Chip-Based Multicores

October 3, 2013 @ 3:00 pm - 4:00 pm

Prof. Vassos Soteriou
Department of Electrical Engineering,
Computer Engineering and Informatics,
Cyprus University of Technology

 

Abstract:

Traffic hotspots, a severe form of congestion, can be caused unexpectedly in a Network-onChip (NoC) due to the immanent spatio-temporal unevenness of application traffic. Hotspots reduce the NoC’s effective throughput, where in the worst-case scenario, network traffic flows can be frozen indefinitely. To alleviate this problematic phenomenon several adaptive routing algorithms employ online load-balancing and/or path load-distributing functions, aiming to reduce the possibility of hotspots arising. Since most are not explicitly hotspot-agnostic, they cannot completely prevent hotspot formation(s) as their reactive capability to hotspots is merely passive. In this talk I will present a pro-active Hotspot-Preventive Routing Algorithm (HPRA) which uses the advance knowledge gained from network-embedded Artificial Neural Network-based (ANN) hotspot predictors to guide packet network routing in mitigating any unforeseen near-future hotspot occurrences. First, these ANNs are trained offline and during multicore operation they gather online statistical data to predict about-to-be-formed hotspots, promptly informing HPRA to take appropriate hotspot-preventing action(s). Next, in a holistic approach, further ANN training is performed with data acquired after HPRA interferes, so as to improve hotspot prediction accuracy; hence, the ANN mechanism does not only predict hotspots, but is also aware of changes that HPRA imposes upon the interconnect infrastructure. Evaluation results across two synthetic traffic patterns, and traffic benchmarks gathered from a chip multiprocessor architecture, show that HPRA can reduce network latency and improve network throughput up to 81% when compared against several existing state-of-the-art congestion-aware routing functions. Hardware synthesis results demonstrate the efficacy of the HPRA mechanism.

 

Bio:

Vassos Soteriou is currently an Assistant Professor in the Department of Electrical Engineering, Computer Engineering and Informatics at the Cyprus University of Technology, located in the city of Lemesos, Cyprus. He received the B.S. and Ph.D. degrees in electrical engineering from Rice University in 2001, and Princeton University in 2006, respectively. His undergraduate studies were entirely funded through a CASP/Fulbright scholarship. Dr. Soteriou is a recipient of a Best Paper Award at the 2004 IEEE International Conference on Computer Design. He is a Member of the IEEE and a Member of HiPEAC, the European Network of Excellence on High Performance and Embedded Architecture and Compilation. He has served on the Technical Committee of several conferences and serves as a regular reviewer for numerous journal and conference proceedings manuscripts of the IEEE and ACM. His research interests lie in interconnection networks, on-chip networks and multi-core architectures, with emphasis on power consumption management methodologies, fault tolerance, micro-architectural performance enhancements, and design-space exploration.

Details

Date:
October 3, 2013
Time:
3:00 pm - 4:00 pm