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CESG Seminar: Breaking the On-Chip Latency Barrier Using Single-Cycle Multi-Hop Networks

April 28 @ 4:10 pm - 5:10 pm

| Free

Dr. Krisha, Georgia Tech

Friday, April 28, 2017 @ 4:10 in Wisenbaker Engineering Building 236C


Abstract: Compute systems are ubiquitous, with form factors ranging from smartphones at the edge to datacenters in the cloud. Chips in all these systems today comprise 10s to 100s of homogeneous/heterogeneous cores or processing elements. Ideally, any pair of these cores communicating with each other should have a dedicated link between them. But this design philosophy is not scalable beyond a few cores; instead chips use a shared interconnection network, with routers at crosses points to facilitate the multiplexing of links across message flows. These routers add multiple cycles of delay at every hop of the traversal. Conventional wisdom says that the latency of any multi-hop network traversal is directly proportional to the number of hops. This can profoundly limit scalability.

In this talk, we challenge this conventional wisdom. We present a network-on-chip (NoC) design methodology called SMART* that enables messages to traverse multiple-hops, potentially all the way from the source to the destination, within a single-cycle, over a NoC with shared links. SMART leverages repeated wires in the datapath, which can traverse 10+ mm at a GHz frequency. We present a reconfiguration methodology to allow different message flows to reserve multiple links (with turns) within one cycle and traverse them in the next. An O (n)-wire SMART provides 5-8X latency reduction across traffic patterns, and approaches the performance of an “ideal” but impractical all-to-all connected O (n^2)-wire network.

We also demonstrate two examples of micro-architectural optimizations enabled by SMART NoCs. The first is locality-oblivious cache organization architecture and the second is a recently demonstrated deep learning accelerator chip called Eyeriss.

*Single-cycle Multi-hop Asynchronous Repeated Traversal


Bio: Tushar Krishna is an Assistant Professor in the School of Electrical and Computer Engineering at Georgia Tech, with an Adjunct appointment in the School of Computer Science. He received a Ph.D. in Electrical Engineering and Computer Science from the Massachusetts Institute of Technology in 2014. Prior to that he received a M.S.E in Electrical Engineering from Princeton University in 2009 and a B.Tech in Electrical Engineering from the Indian Institute of Technology (IIT) Delhi in 2007.

Before joining Georgia Tech in 2015, Dr. Krishna spent a year as a post-doctoral researcher in the VSSAD Group at Intel, Massachusetts and a semester at the LEES IRG at the Singapore-MIT Alliance for Research and Technology.

Dr. Krishna’s research spans the computing stack: from circuits/physical design to microarchitecture to system software. His key focus area is in architecting the interconnection networks and communication protocols for efficient data movement within computer systems, both on-chip and in the cloud.


Host: Dr. Sprintson



April 28, 2017
4:10 pm - 5:10 pm


WEB, Room 236-C
Wisenbaker Engineering Building
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