Room 1034 ETB
David Kadjo (graduate student)
Abstract: For decades, the primary tools in alleviating the “Memory Wall” have been large cache hierarchies and data prefetchers. Both approaches, become more challenging in modern, Chip-multiprocessor (CMP) design. Increasing the last-level cache (LLC) size yields diminishing returns in terms of performance per Watt; given VLSI power scaling trends, this approach becomes hard to justify. These trends also impact hardware budgets for prefetchers. Moreover, in the context of CMPs running multiple concurrent processes, prefetching accuracy is critical to prevent cache pollution effects. These concerns point to the need for a light-weight prefetcher with high accuracy. Existing data prefetchers may generally be classified as low-overhead and low accuracy (Next-n, Stride, etc.) or high-overhead and high accuracy (STeMS, ISB). We propose B-Fetch: a data prefetcher driven by branch prediction and effective address value speculation. B-Fetch leverages control flow prediction to generate an expected future path of the executing application. It then speculatively computes the effective address of the load instructions along that path based upon a history of past register transformations. Detailed simulation using a cycle accurate simulator shows a geometric mean speedup of 23.4% for single-threaded workloads, improving to 28.6% for multi-application workloads over a baseline system without prefetching. We find that B-Fetch outperforms an existing “best-of-class” light-weight prefetcher under single-threaded and multiprogrammed workloads by 9% on average, with 65% less storage overhead.
BIO: David Kadjo is a PhD candidate in the electrical and computer engineering department at Texas A&M University. He received Bachelors in Electrical Engineering and Mathematics from the New Mexico Institute of Mining and Technology in 2005. He, also, received a Masters in Electrical Engineering from the University of Texas at El Paso in 2007.