Room 1034 ETB
Gianfranco Gerosa, PhD
Corporate Memory Organization (CMO)
Abstract: This talk will cover Intel die photos, transistor cross-sections and interconnect details from 90nm planar CMOS to the current 14nm FIN-FET technology. Transistor performance improvements due to mobility enhancement from Source-Drain ‘straining’ and metal gates will be shown; gate leakage reduction due to high-K dielectric will also be shown. Finally, FIN-FET transistor improvements between 22n and 14nm will be highlighted.
Bio: Gianfranco Gerosa has 32 years of experience in the semiconductor industry since obtaining his PhD in electrical engineering from the Ohio State University (OSU) in 1982. He has a BSEE from the Georgia Institute of Technology (1977) and a MSEE from OSU (1980). He started his career at Intel Corporation working on 1.2um CMOS device development. From 1985 he worked on non-volatile, DRAM and SRAMs at MOTOROLA. From 1991 through 1998, he led the PowerPC603 integration team and later took the role of design manager for the PowerPC750 RISC microprocessor. He re-joined Intel to work on high performance desk-top IA32 microprocessor development in Austin, Texas in 1999. Starting in 2004, Gian led path-finding and technology readiness efforts for a low power IA core design which eventually became Intelís 1st ATOM processor product. Gian was involved in the design and silicon debug efforts of a 3rd and 4th generation ATOM-cpu-based SoCs in 32nm and 22nm CMOS. He is currently involved in PROM and Voltage Level Detector design for 14nm and 10nm CMOS as a Principal Engineer. Gian has 14 issued patents, over 25 co-authored papers related to chip design, circuit design, and ESD protection. Gian was a member of the ISSCCís digital sub-committee (1997-1999) where he co-chaired several clocking/logic sessions and was the 1998 JSSC guest editor.
Host: Dr. Khatri