Room 333 WERC (Fishbowl)
Sriram Vangal, Intel labs
Commercial designs currently integrate tens to hundreds of embedded functional and storage blocks in a monolithic SoC, and the number is expected to increase significantly in the near future. The possibility of such high levels of integration in a single chip necessitates the design of high-bandwidth, low-power interconnect architectures. The talk shares key learnings obtained from silicon implementations on two generations of NoCs- the “80-tile Polaris TeraFLOP processor” and the “48-iA core Single-chip cloud-computer” (SCC) with a key focus on improving energy-efficiency in the interconnect. The data confirms that in this age of interconnect-centric VLSI, computing locally is inexpensive but moving information becomes the limiting bottleneck. The discussion presents challenging trends and reviews promising solutions to improving NoC energy-efficiency and provides suggestions for future research.
Bio: Sriram. R. Vangal received the Ph.D. degree in Electrical Engineering from Linköping University, Sweden. He joined Intel Corporation in 1995 and is currently a Principal Research Scientist with Microprocessor Research Labs, Hillsboro, OR, USA. Sriram played a lead role in multi-core CPU development: 80-core, sub-100W “Polaris” TeraFLOPS NoC, the 48-iA core “Rock Creek” single-chip cloud computer (SCC) and more recently the Claremont NTV iA processor. Sriram has published over 25 journal and conference papers including two book chapters on on-die interconnects, and has 18 issued patents with 7 pending in these areas. Sriram serves on VLSI design and NoC Symposium technical program committees.
Host: Dr. Hu