Room 1037 ETB
Graduate Student/ECEN Dept./TAMU
This paper presents a parallel digital VLSI architecture for combined support vector machine (SVM) training and classification. For the first time, cascade SVM, a powerful training algorithm, is leveraged to significantly improve the scalability of hardware-based SVM training and develop an efficient parallel VLSI architecture. The presented architecture achieves excellent scalability by spreading the training workload of a given data set over multiple SVM processing units with minimal communication overhead. Hardware-friendly implementation of the cascade algorithm is employed to achieve low hardware overhead and allow for training over data sets of variable size. In the proposed parallel cascade architecture, a multilayer system bus and multiple distributed memories are used to fully exploit parallelism. In addition, the proposed architecture is rather flexible and can be tailored to realize hybrid use of hardware parallel processing and temporal reuse of processing resources, leading to good tradeoffs between throughput, silicon overhead and power dissipation. Several parallel cascade SVM processors have been designed with a commercial 90-nm CMOS technology, which provide a promising training time speedup and a significant energy reduction compared with the software SVM algorithm running on a 45-nm commercial general-purpose CPU.
BIO: Qian Wang received B.S. in Electrical Engineering from Harbin Institute of Technology in 2009. He worked as a research assistant at University of Kansas to develop novel photonic devices and received M.S in Electrical Engineering in 2012. Currently, he is a PhD student at Texas A&M, working on VLSI hardware implementation of machine learning algorithms.