Loading Events

« All Events

  • This event has passed.

CESG Seminar: Power Minimization in Digital ICs

November 16, 2012 @ 3:00 pm - 4:00 pm

Room 1037 Emerging Technologies Bldg.  (ETB)

Professor Carl Sechen

University of Texas at Dallas

Abstract: A globally optimal Lagrangian relaxation based algorithm was developed that robustly minimizes the total active area (the sum of all transistor widths), thus minimizing power, needed for any feasible delay target assuming arbitrary (continuous) cell sizes. An accurate table-lookup delay model was developed from the pre-characterized industrial standard cell library data by making a formal extension to the concept of logical effort which enables optimization of nMOS and pMOS sizes of a cell separately. Then, a new delay-bounded dynamic programming based algorithm was developed that maps the continuous sizes to the discrete sizes available in the standard cell library which achieves active area versus delay results close to the continuous sizing results. Next, a new threshold voltage (VT) selection algorithm was developed that minimizes leakage power while strictly preserving the delay constraint. Finally, a new power optimization flow was developed that utilizes separate synthesis and physical cell libraries. The physical library consists of the most power efficient cells whereas the synthesis library includes additional complex cells, which are compound compositions of cells from the physical library. After using state-of-the-art commercial synthesis, the application of the new cell size selection tool resulted in a 36% reduction (on average) in active area. The application of the new VT selection algorithm combined with the near optimal cell size selection tool demonstrated a leakage power reduction of 70% (on average) for single-VT synthesis and 37% (on average) for multi-VT synthesis of industrial designs. The dual library approach resulted in a 13% reduction in active area for the same delay compared to a 40nm industrial library. All the algorithms are efficient, with an ability to handle large commercial designs.

BIO: Carl Sechen received the B.E.E. degree from the University of Minnesota, Minneapolis, the M.S. degree from the Massachusetts Institute of Technology (MIT), Cambridge, and the Ph.D. degree from the University of California (UC), Berkeley in 1986.

Starting in 1986, he was an Assistant and then Associate Professor in the Department of Electrical Engineering, Yale University, New Haven, CT. From June 1992 through July 2005 was an Associate Professor and then Professor in the Department of Electrical Engineering at the University of Washington, Seattle, WA. Since August 2005 he is a Professor in the Electrical Engineering Department at the University of Texas at Dallas.

Prof. Sechen was named an IEEE Fellow in 2002 for contributions in placement and routing of integrated circuits. He received the Distinguished Teacher of the Year Award, Dept. of Electrical Engineering, Erik Jonsson School of Engineering and Computer Science, University of Texas at Dallas in 2008. In addition, he received the 2002 Outstanding Research Advisor Award from the Dept. of Electrical Engineering at the Univ. of Washington. Prof. Carl Sechen received the Semiconductor Research Corporation’s Inventor’s Recognition Award” in 2001 for Output Prediction Logic. He also received “SRC Technical Excellence Award” in 1994 for contributions in the area of integrated circuit layout, and the “SRC Inventor’s Award” in October 1988. Prof. Sechen also received the Outstanding Research Project Award from the NSF Center for the Design of Analog and Digital Integrated Circuits (CDADIC) in 2002.

Dr. Sechen developed the TimberWolf placement and routing package that was used at more than 20 companies and more than 25 universities.  In a paper presented at the recent February 2006 International Solid- State Circuits Conference (ISSCC), Dr. Sechen described a 64-bit adder fabricated using the 130nm IBM process technology which was twice as fast and used half the energy compared to the best previously reported adder.

Prof. Sechen directs the Nanometer Design Laboratory at UT Dallas, which includes six Ph.D. students and one post-doctoral researcher. Prof. Sechen has graduated 25 Ph.D. students. He has authored one book, two patents, and authored or coauthored 164 research papers. He is a co-founder of InternetCAD.com, Inc., a placement and routing tool vendor.

His research interests center primarily on the design and computer-aided design of digital integrated circuits. In particular, high speed and low power digital IC design, including power efficient and very high throughput DSP network design. Active work includes standard cell library optimization for maximum power efficiency. Also, optimal gate size and threshold voltage selection. Finally, highly reliable, very low area overhead and power efficient asynchronous logic design for future process technologies operating at very low voltages.

Host:  Dr. Hu

 

 

 

Details

Date:
November 16, 2012
Time:
3:00 pm - 4:00 pm