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CESG Seminar: Ternary CAM Design for IP Routing using Floating Gate Transistors

February 6, 2015 @ 3:55 pm - 5:00 pm

Room 1037 ETB

Viacheslav Fedorov (graduate student)
ECEN Dept./TAMU

Abstract:
Viacheslav will be presenting a novel Ternary Content-addressable Memory (TCAM) design which is based on the use of floating-gate (flash) transistors. TCAMs are extensively used in high speed IP networking, and are commonly found in routers in the internet core. Traditional TCAM ICs are built using CMOS devices, and a single TCAM cell utilizes 17 transistors. In contrast, the proposed TCAM cell utilizes only 2 flash transistors, thereby significantly reducing circuit area. The chip-level architecture of the TCAM IC will be covered briefly, with main focus being on the TCAM block which does fast parallel IP routing table lookup. The flash based TCAM block is simulated in SPICE, and has a significantly lowered area compared to a CMOS based TCAM block, with a speed that can meet current (∼400 Gb/s) data rates that are found in the internet core.

BIO: Viacheslav Fedorov has received B.S. and M.S. degrees in Applied Mathematics from Moscow Institute of Physics and Technology in 2007 and 2009, respectively.
He worked at MCST (Moscow Center for SPARC Technologies) as a junior hardware engineer. Currently, he is a graduate student at Texas A&M, working on memory systems and architectures. Particular interests are CPU last-level caches, OS scheduling, and Virtualization.

Details

Date:
February 6, 2015
Time:
3:55 pm - 5:00 pm