Room 1034 ETB
Cyprus University of Technology
Moore’s Law scaling is continuing to yield even higher transistor density with each succeeding process generation, leading to today’s multi-core Chip Multi-Processors (CMPs) with tens or even hundreds of interconnected cores or tiles. Unfortunately, deep sub-micron CMOS process technology is marred by increasing susceptibility to wearout. Prolonged operational stress gives rise to accelerated wearout and failure, due to several physical failure mechanisms, including Hot Carrier Injection (HCI) and Negative Bias Temperature Instability (NBTI). Each failure mechanism correlates with different usage-based stresses, all of which can eventually generate permanent faults. While the wearout of an individual core in many core CMPs may not necessarily be catastrophic for the entire parallel-processing system, a single fault in the inter-processor Networkon-Chip (NoC) fabric could render the entire chip useless, as it could lead to protocol-level deadlocks, or even partition away vital components such as the memory controller or other critical I/O. In this talk I will discuss NoC router critical path models developed for HCI- and NBTI-induced wearout due to stresses caused by realistic workloads, and how they are applied onto the on-chip interconnect microarchitecture. A key finding from this modeling being that, counter to prevailing wisdom, wearout in the CMP on-chip interconnect is correlated with lack of load observed in the NoC routers, rather than high load. I will then present a novel wearout-decelerating scheme in which routers under low load have their wearout-sensitive components exercised, without significantly impacting cycle time, pipeline depth, area or power consumption of the overall router. I will subsequently show that the proposed design yields a 13.8×-65× increase in CMP lifetime.
Bio: Vassos Soteriou is currently an Assistant Professor in the Department of Electrical Engineering, Computer Engineering and Informatics at the Cyprus University of Technology, located in the city of Lemesos, Cyprus. He received the B.S. and Ph.D. degrees in electrical engineering from Rice University in 2001, and Princeton University in 2006, respectively. His undergraduate studies were entirely funded through a CASP/Fulbright scholarship. Dr. Soteriou is a recipient of a Best Paper Award at the 2004 IEEE International Conference on Computer Design. He is a Member of the IEEE and a Member of HiPEAC, the European Network of Excellence on High Performance and Embedded Architecture and Compilation. He has served on the Technical Committee of several conferences and serves as a regular reviewer for numerous journal and conference proceedings manuscripts of the IEEE and ACM. His research interests lie in interconnection networks, on-chip networks and multi-core architectures, with emphasis on power consumption management methodologies, fault-tolerance, micro-architectural performance enhancements, and design-space exploration.