Room 1037 (Emerging Technologies Building- ETB)
Dr. Sachin Sapatnekar
University of Minnesota
As CMOS technologies have shrunk to the scale of tens of nanometers, reliability and aging problems have emerged as a major challenge. These issues promises to grow increasingly troublesome in the future. There has been tremendous progress in developing new methods for modeling and diagnosing reliability at the level of individual transistors, but much less work on propagating these models to higher levels of abstraction to predict the reliability of larger circuits. This talk will provide a basic introduction to various circuit aging mechanisms and will then discuss research that develops computer-aided design techniques for estimating and enhancing the reliability of large digital circuits, with specific emphasis on failures due to phenomena such as bias temperature instability, gate oxide breakdown, and hot carrier injection, examining solutions that could practically be applied to analyze or improve the lifetime of a design.
Bio: Sachin Sapatnekar received his Ph.D. from the University of Illinois at Urbana-Champaign in 1992. He is currently at the University of Minnesota, where he holds the Distinguished McKnight University Professorship and the Henle Professorship in ECE. His research is related to developing CAD techniques for the analysis and optimization of circuit performance. He served as General Chair for the 2010 ACM/IEEE Design Automation Conference (DAC) and is currently Editor-in-Chief of the IEEE Transactions on CAD. He has received several conference Best Paper awards, and the SRC Technical Excellence award, and is an IEEE fellow.
Host: Dr. Jiang Hu