Room 333 (fishbowl)
Department of Electrical and Computer Engineering
Missouri University of Science and Technology
Abstract: Conventional three-dimensional integrated circuits (3D ICs) stack multiple dies vertically for higher integration density, shorter wirelength, smaller footprint, faster speed and lower power consumption. However, the through-silicon-via (TSV), as an enabling technique in 3D ICs, is typically 5-10x larger than standard cells. This significantly reduces the benefits brought by the vertical integration. As a result, most 3D stacking today is limited at the architecture-level such as memory-on-logic. On the other hand, monolithic 3D ICs can significantly reduce the TSV size, but are generally believed to be expensive to fabricate. It is also unclear how much benefit can be achieved by monolithic 3D integration over the conventional die stacking. In this talk, we will discuss a novel technique for monolithic 3D integration which utilizes existing fabrication processes, and how it would drastically change the design freedom of 3D integration through the case study of an 8-bit ripple carry adder.
Bio: Dr. Yiyu Shi received his B.S. degree from Tsinghua University in 2005, the M.S and Ph.D. degree from the University of California, Los Angeles in 2007 and 2009 respectively. In Sept. 2010, he joined the faculty of ECE Dept. at Missouri University of Science and Technology (formerly Univ. of Missouri, Rolla), and is currently the site associate director of NSF I/UCRC Net-Centric Software and Systems Center. He has served on the technical program committee of several top conferences including ICCAD, ICCD, ASPDAC and ISPD. His research interest include advanced design and test technologies for 3D ICs, and smart grid applications. In recognition of his research, five of his papers have been nominated for the Best Paper Award in top conferences. He was also the recipient of the IBM Invention Achievement Award in 2009. For more details, please visit http://ece.mst.edu/~yshi