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March 2017
Free

CESG TELESEMINAR: “Collaborative Road Freight Transport”

March 30 @ 2:30 pm - 4:00 pm

“Collaborative Road Freight Transport” Karl H. Johansson –  KTH Royal Institute of Technology   Abstract: Freight transportation is of outmost importance for our society. Road transporting accounts for about 26% of all energy consumption and 18% of greenhouse gas emissions in the European Union. Goods transport in the EU amounts to 3.5 trillion ton-km per year with 3 million people employed in this sector, whereas people transport amounts to 6.5 trillion passenger-km with 2 million employees. Despite the influence the transportation system has on our energy consumption and the environment, individual long-haulage trucks with no real-time coordination or global optimization mainly do road goods transportation. In this talk, we will discuss how modern information and communication technology supports cyber-physical transportation system architecture with an integrated logistic system coordinating fleets of trucks traveling together in vehicle platoons. From the reduced air drag, platooning trucks traveling close together can save more than 10% of their fuel consumption. Control and estimation challenges and solutions on various level of this transportation system will be presented. It will be argued that a system architecture utilizing vehicle-to-vehicle and vehicle-to-infrastructure communication enable optimal and safe control of individual trucks as well as optimized vehicle fleet collaborations and new markets. Extensive experiments done on European highways will illustrate system performance and safety requirements. The presentation will be based on joint work over the last ten years with collaborators at KTH and at the truck manufacturer Scania.   Bio: Karl H. Johansson is Director of the Stockholm Strategic Research Area ICT The Next Generation and Professor at the School of Electrical Engineering, KTH Royal Institute of Technology. He received MSc and PhD degrees in Electrical Engineering from Lund University. He has held visiting positions at UC Berkeley, Caltech, NTU, HKUST Institute of Advanced Studies, and NTNU. His research interests are in networked control systems, cyber-physical systems, and applications in transportation, energy, and automation. He is a member of the IEEE Control Systems Society Board of Governors and the European Control Association Council. He has received several best paper awards and other distinctions, including a ten-year Wallenberg Scholar Grant, a Senior Researcher Position with the Swedish Research Council, and the Future Research Leader Award from the Swedish Foundation for Strategic Research. He is Fellow of the IEEE and IEEE Distinguished Lecturer.

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April 2017
Free

CESG Seminar: Breaking the On-Chip Latency Barrier Using Single-Cycle Multi-Hop Networks

April 28 @ 4:10 pm - 5:10 pm
WEB, Room 236-C,
Wisenbaker Engineering Building
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Dr. Krisha, Georgia Tech Friday, April 28, 2017 @ 4:10 in Wisenbaker Engineering Building 236C   Abstract: Compute systems are ubiquitous, with form factors ranging from smartphones at the edge to datacenters in the cloud. Chips in all these systems today comprise 10s to 100s of homogeneous/heterogeneous cores or processing elements. Ideally, any pair of these cores communicating with each other should have a dedicated link between them. But this design philosophy is not scalable beyond a few cores; instead chips use a shared interconnection network, with routers at crosses points to facilitate the multiplexing of links across message flows. These routers add multiple cycles of delay at every hop of the traversal. Conventional wisdom says that the latency of any multi-hop network traversal is directly proportional to the number of hops. This can profoundly limit scalability. In this talk, we challenge this conventional wisdom. We present a network-on-chip (NoC) design methodology called SMART* that enables messages to traverse multiple-hops, potentially all the way from the source to the destination, within a single-cycle, over a NoC with shared links. SMART leverages repeated wires in the datapath, which can traverse 10+ mm at a GHz frequency. We present a reconfiguration methodology to allow different message flows to reserve multiple links (with turns) within one cycle and traverse them in the next. An O (n)-wire SMART provides 5-8X latency reduction across traffic patterns, and approaches the performance of an “ideal” but impractical all-to-all connected O (n^2)-wire network. We also demonstrate two examples of micro-architectural optimizations enabled by SMART NoCs. The first is locality-oblivious cache organization architecture and the second is a recently demonstrated deep learning accelerator chip called Eyeriss. *Single-cycle Multi-hop Asynchronous Repeated Traversal   Bio: Tushar Krishna is an Assistant Professor in the School of Electrical and Computer Engineering at Georgia Tech, with an Adjunct appointment in the School of Computer Science. He received a Ph.D. in Electrical Engineering and Computer Science from the Massachusetts Institute of Technology in 2014. Prior to that he received a M.S.E in Electrical Engineering from Princeton University in 2009 and a B.Tech in Electrical Engineering from the Indian Institute of Technology (IIT) Delhi in 2007. Before joining Georgia Tech in 2015, Dr. Krishna spent a year as a post-doctoral researcher in the VSSAD Group at Intel, Massachusetts and a semester at the LEES IRG at the Singapore-MIT Alliance for Research and Technology. Dr. Krishna’s research spans the computing stack: from circuits/physical design to microarchitecture to system software. His key focus area is in architecting the interconnection networks and communication protocols for efficient data movement within computer systems, both on-chip and in the cloud.   Host: Dr. Sprintson FREE SNACKS

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