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WEB, Room 236-C

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Wisenbaker Engineering Building
http://cesg.tamu.edu

Upcoming Events

April 2017
Free

CESG Seminar: “Breaking the On-Chip Latency Barrier Using Single-Cycle Multi-Hop Networks”

April 28 @ 4:10 pm - 5:10 pm

Dr. Tushar Krisha of Georgia Tech Abstract:  Compute systems are ubiquitous, with form factors ranging from smartphones at the edge to datacenters in the cloud. Chips in all these systems today comprise 10s to 100s of homogeneous/heterogeneous cores or processing elements. Ideally, any pair of these cores communicating with each other should have a dedicated link between them. But this design philosophy is not scalable beyond a few cores; instead chips use a shared interconnection network, with routers at crosses points to facilitate the multiplexing of links across message flows. These routers add multiple cycles of delay at every hop of the traversal. Conventional wisdom says that the latency of any multi-hop network traversal is directly proportional to the number of hops. This can profoundly limit scalability. In this talk, we challenge this conventional wisdom. We present a network-on-chip (NoC) design methodology called SMART* that enables messages to traverse multiple-hops, potentially all the way from the source to the destination, within a single-cycle, over a NoC with shared links. SMART leverages repeated wires in the datapath, which can traverse 10+ mm at a GHz frequency. We present a reconfiguration methodology to allow different message flows to reserve multiple links (with turns) within one cycle and traverse them in the next. An O (n)-wire SMART provides 5-8X latency reduction across traffic patterns, and approaches the performance of an “ideal” but impractical all-to-all connected O (n^2)-wire network. We also demonstrate two examples of micro-architectural optimizations enabled by SMART NoCs. The first is locality-oblivious cache organization architecture and the second is a recently demonstrated deep learning accelerator chip called Eyeriss. *Single-cycle Multi-hop Asynchronous Repeated Traversal Bio:  Tushar Krishna is an Assistant Professor in the School of Electrical and Computer Engineering at Georgia Tech, with an Adjunct appointment in the School of Computer Science. He received a Ph.D. in Electrical Engineering and Computer Science from the Massachusetts Institute of Technology in 2014. Prior to that he received a M.S.E in Electrical Engineering from Princeton University in 2009 and a B.Tech in Electrical Engineering from the Indian Institute of Technology (IIT) Delhi in 2007. Before joining Georgia Tech in 2015, Dr. Krishna spent a year as a post-doctoral researcher in the VSSAD Group at Intel, Massachusetts and a semester at the LEES IRG at the Singapore-MIT Alliance for Research and Technology. Dr. Krishna’s research spans the computing stack: from circuits/physical design to microarchitecture to system software. His key focus area is in architecting the interconnection networks and communication protocols for efficient data movement within computer systems, both on-chip and in the cloud.   Tele-seminar in 236C @ 4:10 p.m. Host: Dr. Sprintson FREE SNACKS

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May 2017
Free

CESG Seminar: “Trustworthy Integrated Circuit Design”

May 5 @ 11:30 am - 12:30 pm

“Trustworthy Integrated Circuit Design” Abstract: Designers use third-party intellectual property (IP) cores and outsource various steps in their integrated circuit (IC) design and manufacturing flow. As a result, security vulnerabilities have been emerging, forcing IC designers and end users to reevaluate their trust in ICs. If an attacker gets hold of an unprotected IC, attacks such as reverse-engineering the IC and piracy are possible. Similarly, if an attacker gets hold of an unprotected design, insertion of malicious circuits in the design and IP piracy are possible. To thwart these and similar attacks, we have developed three defenses: IC camouflaging, logic encryption, and split manufacturing. IC camouflaging modifies the layout of certain gates in the IC to deceive attackers into obtaining an incorrect netlist, thereby, preventing reverse engineering by a malicious user. Logic encryption implements a built-in locking mechanism on ICs to prevent reverse engineering and IP piracy by a malicious foundry and user.  Split manufacturing splits the layout and manufactures different metal layers in two separate foundries to prevent reverse engineering and piracy by a malicious foundry. We then describe how these techniques are enhanced by using provably-secure techniques thereby leading to trustworthy ICs. Bio: Jeyavijayan (JV) Rajendran is an Assistant Professor in the Department of Electrical and Computer Engineering at the University of Texas at Dallas. He obtained his Ph.D. degree in the Electrical and Computer Engineering Department at New York University in August 2015. His research interests include hardware security and emerging technologies. His research has won the NSF CAREER Award in 2017, the ACM SIGDA Outstanding Ph.D. Dissertation Award in 2017, and the Alexander Hessel Award for the Best Ph.D. Dissertation in the Electrical and Computer Engineering Department at NYU in 2016. He has won three Student Paper Awards (ACM CCS 2013, IEEE DFTS 2013, and IEEE VLSI Design 2012); four ACM Student Research Competition Awards (DAC 2012, ICCAD 2013, DAC 2014, and the Grand Finals 2013); Service Recognition Award from Intel; Third place at Kaspersky American Cup, 2011; and Myron M. Rosenthal Award for Best Academic Performance in M.S. from NYU, 2011. He organizes the annual Embedded Security Challenge, a red-team/blue-team hardware security competition and has co-founded Hack@DAC, a student security competition co-located with DAC. He is a member of IEEE and ACM.   FREE SNACKS

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