Dr. Gratz Presents “Use-it or Lose-it”

Dr. Paul Gratz, Assistant Professor of Electrical and Computer Engineering and member of Computer Engineering and Systems Group presented, “Use-it or Lose-it: Wear Out and Lifetime in Future Chip-Multiprocessor Interconnect”, last Tuesday for the AMSC Seminar series. In his talk, Dr. Gratz drew attention to a prevailing problem among multi-core Chip Multi-Processors (CMPs). Premature wearout in these CMPs is causing faults that can yield catastrophic results. Seeking to remedy this issue, Dr. Gratz explores solutions to decelerate the wear of these chips.

As processor vendors continue to pack higher volumes of transistors into chips, the number of interconnected cores in CMPs has grown into the hundreds. With such a large number of processor cores, core wearout becomes less critical as each core contributes less to the overall throughput of the chip. However, failure of the interconnect between cores can be critical with the potential to render the chip useless. These faults are physical by nature, often resulting from processes like Hot Carrier Injection (HCI) and Negative Bias Temperature Instability (NBTI).

To solve this problem, Dr. Gratz focuses on modeling the deterioration due to the HCI and NBTI failure processes as caused by an application workload. Dr. Gratz discovered that counter to intuition, high loads did not cause failure in these devices. Rather, low loads were leading to accelerated wearout and failure.

This discovery allowed Dr. Gratz to come up with a decelerating scheme that would essentially give the interconnect routers a, “work-out,” to improve their lifetime. The suggested process increased the overall life expectancy of the CMP by 14-65X its original projection.

Dr. Gratz researches energy efficient and reliable design in the context of high performance computer architecture, processor memory systems, and on-chip interconnection networks. He has received both B.S. and M.S degrees in Electrical Engineering from The University of Florida. He worked at Intel as a design engineer for 5 years, and has since received his Ph.D. in Electrical and Computer Engineering from the University of Texas at Austin. Dr. Gratz has received several awards including, “Best Papers from IEEE Computer Architecture Letters in 2011,” for his paper, “B-Fetch: Branch Prediction Directed Prefetching for In-Order Processors,” in which he was one of four winners. Dr. Gratz also co-authored, “An Evaluation of the TRIPS Computer System,” which received the best paper award at ASPLOS ’09.