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Spring Graduation!
✿ We are pleased to announce the following 54 MS and 3 PhD students graduating from ECE’s Computer Engineering Systems Group on Saturday, May 13! We are grateful they were part of our program, and we hope they are leaving with strong skills and confidence as they pursue their careers and go out to make the world a better, safer, and happier place! They will be putting to use their skills in cyber security, virtual reality, robotics, VLSI, data science, networking, architecture & systems, and much more! They should be very valuable to their employers for decades to come!
Most started our program in December 2021. Some came after deferring the year before due to the pandemic. And, getting to know each other was a bit more challenging as we slowly returned to in-person events, classes and gatherings. Nevertheless, we hope they will have fond memories of their time in Aggieland and will hold these experiences in their hearts. ♥
If you have a chance, please wish the following a well-deserved “Congratulations” !
Doctorate Degrees
Dr. Gino Chacon (advisor: Paul Gratz)
Dr. Kaan Sel (advisor: Roozbeh Jafari)
Dr. Jinhyun So (advisor: Mi Lu)
Master of Science Degrees
Meghana Jaysing Amup
Shabarish Babu Badavanahally
Dharmendra Baruah
Aroma Bhat (^◡^ )
Tejasri Swaroop Boppana
Xiaohai Chen
Sai Namith Garapati
Meghna Manoj Ghole
Amith Gopi ★
Sudharsan Govardan
Hao Guo (ˆ▿ˆc)
Harshit Gupta
Divya Shrikant Hegde
Abby Pallathattayil Joby
Anirudh Kashyap
Pushp Khatter
Sri Hari Pada Chandanam Kodi
Aditya Dilip Kothar ✯
Natarajan Krishnamoorthy
Rajesh Sai Kudipudi
Velmurugan Mohan Krishnapuram
Jyothi Swaroopa Myneedi
Saurabh Nalkunda Kyathaplar
Shobith Narayanan
Punarvi Pallamreddy
Abhijay Kumar Pandit
Balaji Aathithan Paranthaman
Sanjana Patri (っ＾▿＾)💨
Swarna Srikanth Prabhu
Ajin Thankachan Pullan
Shanmuga Srinivas Puthalapattu
Kezhuo Qi
Gokul Raghunathan
Nitin Kasshyap Ragothaman
Amritha Rajagopalan
Mridhula Ramesh
Rajendra Prasad Sahu ٩(˘◡˘)۶
Kavya Santha Kumar
Allen Sebastian
Vaibhavi Shanbhag
Bhavesh Hariom Sharma
Prachi Sharma
Digvijay Singh
Shashi Preetham Sreebhashyam
Vamsi Tallam (̶◉͛‿◉̶)
Kaushal Prudhvi Raj Tungaturthy
Mohammadi Turabbhai
Suryateja Vadlamani
Sreemayee Venigalla
Chun Sheng Wu
Gayathri Narayana Yegna Narayanan💨
Siri Chandana Yeshala
Chongzhi Zhao (❛‿❛ )
Zanbo Zhu
Please celebrate yourselves too graduates! You have done a lot over the last few years and deserve to feel pride in all you overcame, endured, discovered and produced! 👍
Best wishes from all of us in CESG!
Congratulations Dr. Hu!
CESG’s Jiang Hu has a new publication: Machine Learning Applications in Electronic Design Automation by himself and Dr. Haoxing Ren.
This book covers a wide range of the latest research on ML applications in electronic design automation (EDA), including analysis and optimization of digital design, analysis and optimization of analog design, as well as functional verification, FPGA and system level designs, design for manufacturing, and design space exploration. The ML techniques covered in this book include classical ML, deep learning models such as convolutional neural networks, graph neural networks, generative adversarial networks and optimization methods such as reinforcement learning and Bayesian optimization.
More information at https://www.barnesandnoble.com/w/machine-learning-applications-in-electronic-design-automation-haoxing-ren/1141727406?ean=9783031130748
Dr. P.R. Kumar – IEEE Alexander Graham Bell Medal
Dr. Kumar is the 2022 recipient of one of the Institute of Electrical and Electronics Engineers’ (IEEE) most prestigious honors — the IEEE Alexander Graham Bell Medal. It is the highest award by IEEE in communications and networking. Kumar was recognized for his seminal contributions to the modeling, analysis and design of wireless networks.
For more, go to https://engineering.tamu.edu/news/2021/12/kumar-awarded-institute-of-electrical-and-electronics-engineers-medal.html.
Congratulations Dr. Kumar!
Dr. JV Rajendran – 2022 Young Investigator Award Recipients
Dr. JV Rajendran has won the 2022 Young Investigator Award from the Office of Naval Research Science & Technology!
His research work is titled Steel Wool: Next-Generation Hardware Fuzzers and addresses the area of Cyber Security and Complex Software Systems.
Congratulations JV!
Best Paper Award – IEEE: Drs. Yasin and Rajendran
Congratulations to former CESG Post-Doc Dr. Muhammad Yasin and Dr. JV Rajendran! Their 2020 paper “Removal Attacks on Logic Locking and Camouflaging Techniques” won a Best Paper Award from the Computer Society Publications Board and IEEE Transactions on Emerging Topics in Computing.
Congratulations Dr. Karan Watson!
Dr. Karan Watson, Regents Professor, was awarded the 2021 American Society for Engineering Education (ASEE) Lifetime Achievement Award in Engineering Education. Dr. Watson was recognized for her pioneering leadership and sustained contributions to education in the fields of engineering and engineering technology.
For the full article or a more in-depth look at her work, please visit: Texas A&M Engineering News and Dr. Watson’s Google Scholar Profile
Past Recipients
2012 Richard M. Felder
2014 James E. Stice
2015 Karl A. Smith
2016 Russ Pimmel
2018 James L. Melsa
2019 K.L. DeVries
2020 Don P. Giddens
2021 Karan L. Watson
CESG Former Student Shiyan Hu Elected to European Academy of Sciences and Arts
CESG former student, Shiyan Hu, who received his Ph.D. in Computer Engineering in 2008, has been elected as a Member for European Academy of Sciences and Arts for his significant contributions to Design, Optimization, and Security of Cyber-Physical Systems.
European Academy of Sciences and Arts currently has about 2,000 members, including 34 Nobel Prize Laureates, who are world leading scientists, artists, and practitioners of governance, with expertise ranging from Natural Sciences, Medicine, Technical & Environmental Sciences, Humanities, to Social Sciences. Academy members, who are dedicated to innovative research, international collaboration as well as the exchange and dissemination of knowledge, are elected based on their outstanding achievements.
Shiyan Hu is a professor and the Chair in Cyber-Physical System Security and Director of Cyber Security Academy at University of Southampton. He has published more than 150 refereed papers in the area of Cyber-Physical Systems, Cyber-Physical System Security, and VLSI Computer Aided Design, where most of his journal articles appeared in IEEE/ACM Transactions. He is an ACM Distinguished Speaker, an IEEE Systems Council Distinguished Lecturer, a recipient of the 2017 IEEE Computer Society TCSC Middle Career Researcher Award, and a recipient of the 2014 U.S. National Science Foundation CAREER Award. His publications have received distinctions such as the 2018 IEEE Systems Journal Best Paper Award, the 2017 Keynote Paper in IEEE Transactions on Computer-Aided Design, the Front Cover Paper in IEEE Transactions on Nanobioscience in March 2014, multiple Thomson Reuters ESI Highly Cited Papers/Hot Papers, etc. His ultra-fast slew buffering technique has been widely deployed in the industry for designing over 50 microprocessor and ASIC chips such as IBM flagship chips POWER 7 and 8.
He is a well-recognized international leader in his field. He is chairing the IEEE Technical Committee on Cyber-Physical Systems, leading IET Cyber-Physical Systems: Theory & Applications, and chaired the 2020 Editor-in-Chief Search Committee Chair for ACM TODAES. He has served as an Associate Edito
r for 5 IEEE/ACM Transactions such as IEEE TCAD, IEEE TII and ACM TCPS and as a Guest Editor for various IEEE/ACM journals such as Proceedings of the IEEE and IEEE Transactions on Computers. He is an Elected Member of the European Academy of Sciences and Arts, a Fellow of IET, and a Fellow of British Computer Society.
Shiyan Hu says: “I am delighted to be elected as a Member of European Academy of Sciences and Arts. It is a unique honor in recognition of my research accomplishments and international leadership in my research fields. After many years following my graduation, I still feel very grateful to the education I received from Texas A&M’s Computer Engineering Group and research experience with my Ph.D. advisor Professor Jiang Hu. These were pivotally helpful for me to contribute significantly to my fields.”
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Agricultural Blue Legacy Award
Congratulations to Dr. Jiang Hu and team for receiving the Agricultural Blue Legacy Award this March.
They developed a center pivot automation and control system known as CPACS. This contributes to water conservation in the field of agriculture. To learn more, go to http://www.hpwd.org/newswire/2021/3/18/amarillo-water-management-team-honored.
The team is referred to as the “Amarillo Water Management Team” and includes:
Dr. Hongxin Kong, CEEN, PhD Graduate
Jianfeng Song, CEEN, PhD Candidate
Dr. Justin Sun, CEEN, PhD Graduate
Dr. Yanxiang Yang, CEEN, PhD Graduate
Dr. Jiang Hu, co-director of graduate programs in the Texas A&M Department of Electrical and omputer Engineering at College Station;
Dr. Gary Marek, U.S. Department of Agriculture-Agricultural Research Service agricultural engineer at Bushland;
Thomas Marek, AgriLife Research senior research engineer at Amarillo;
Dr. Dana Porter, Texas A&M AgriLife Extension Service program leader in the Department of Biological and Agricultural Engineering at Lubbock; and
Dr. Qingwu Xue, AgriLife Research crop stress physiologist at Amarillo.
Thank you Amarillo Water Management Team for improving our world with your projects!
Pic 1: Dr. Hongxin Kong
Pic 2: Dr. Jiang Hu & Dr. Yanxiang Yang
Pic 3: Dr. Hongxin Kong
Feature Pic: Yanxiang Yang, Thomas Marek & Justin Sun
Congratulations Dr. Hu!
CESG’s Jiang Hu has a new publication: Machine Learning Applications in Electronic Design Automation by himself and Dr. Haoxing Ren.
This book covers a wide range of the latest research on ML applications in electronic design automation (EDA), including analysis and optimization of digital design, analysis and optimization of analog design, as well as functional verification, FPGA and system level designs, design for manufacturing, and design space exploration. The ML techniques covered in this book include classical ML, deep learning models such as convolutional neural networks, graph neural networks, generative adversarial networks and optimization methods such as reinforcement learning and Bayesian optimization.
More information at https://www.barnesandnoble.com/w/machine-learning-applications-in-electronic-design-automation-haoxing-ren/1141727406?ean=9783031130748
CESG Seminar – Dr. Joshua Peeples
Friday, September 2, 2022
10:20 – 11:10 a.m. (CST)
ETB 1020 – **In-person** (or by Zoom for those receiving emails)
Dr. Joshua Peeples
ACES Faculty Fellow & Visiting Assistant Professor, Texas A&M University, Electrical & Computer Engineering
Title: “Statistical Texture Feature Learning for Image Analysis”
Talking Points:
- Convolutional neural networks are biased towards structural textures
- Histogram layer(s) provide statistical context within deep learning models to improve performance
Abstract
Feature engineering often plays a vital role in the fields of computer vision and machine learning. A few common examples of engineered features include histogram of oriented gradients (HOG), local binary patterns (LBP), and edge histogram descriptors (EHD). Features such as pixel gradient directions and magnitudes for HOG, encoded pixel differences for LBP, and edge orientations for EHD are aggregated through histograms to extract texture information. However, the process of designing handcrafted features can be difficult and time consuming. Artificial neural networks (ANNs) such as convolutional neural networks (CNNs) have performed well in various applications such as facial recognition, semantic segmentation, object detection, and image classification through automated feature learning.
A new histogram layer is proposed to learn features and maximize the performance of ANNs for statistical texture analysis. Current approaches using ANNs or handcrafted features do not perform well for some texture applications due to inherent problems within texture datasets (e.g., high intrinsic dimensionality, large intra-class variations) and limitations in methods that use handcrafted and/or deep learning features. The proposed approach is a novel method to synthesize both neural and traditional features into a single pipeline. The histogram layer can estimate bin centers and widths through the backpropagation of errors to aggregate the features from the data while also maintaining spatial information. The improved performance of each network with the addition of histogram layer(s) demonstrates the potential for the use of this new element within ANNs.
Biography
Dr. Joshua Peeples is an ACES Faculty Fellow and Visiting Assistant Professor in the Department of Electrical and Computer Engineering at Texas A&M University. Dr. Peeples received his Bachelor of Science degree in electrical engineering with a minor in mathematics from the University of Alabama at Birmingham. He earned his Ph.D. in the Department of Electrical and Computer Engineering at the University of Florida with Dr. Alina Zare. During his Ph.D. studies, Dr. Peeples developed and refined novel deep learning methods for texture characterization, segmentation, and classification. Dr. Peeples’ current research seeks to extend his dissertation work and explore new aspects such as developing algorithms for explainable AI and various real-world applications in other domains (e.g., biomedical, agriculture). These methods can then be applied toward automated image understanding, object detection, and classification. Dr. Peeples has been recognized with several awards, including the Florida Education Fund’s McKnight Doctoral Fellowship and National Science Foundation Graduate Research Fellowship. In addition to research and teaching, Dr. Peeples is dedicated to service and advocacy for students at the university and in the community.
More information on Dr. Peeples at https://engineering.tamu.edu/electrical/profiles/peeples-joshua.html
Please join on Friday, 9/2/22 at 10:20 a.m. in ETB 1020.
CESG Seminar: Dr. Bo Yuan
Friday, January 25, 2021
4:10 – 5:00 p.m.
via Zoom (link below)
Dr. Bo Yuan
Asst. Professor, Dept. of Electrical & Computer Engineering, Rutgers University
Title: “Algorithm and Hardware Co-Design for Efficient Deep Learning: Sparse and Low-rank Perspective”
Talking Points
- Algorithm and hardware co-design for structured and unstructured deep neural networks
- Algorithm and hardware co-design for high-order tensor decomposition-based deep neural networks
Abstract
In the emerging artificial intelligence era, deep neural networks (DNNs), a.k.a. deep learning, have gained unprecedented success in various applications. However, DNNs are usually storage intensive, computation intensive and very energy consuming, thereby posing severe challenges on the future wide deployment in many application scenarios, especially for the resource-constraint low-power IoT application and embedded systems. In this talk, I will introduce the algorithm/hardware co-design works for energy-efficient DNN in my group, from both the sparse and low-rank perspectives. First, I will show the benefit of using structured and unstructured sparsity of DNN for designing low-latency and low-power DNN hardware accelerators. In the second part of my talk, I will present an algorithm/hardware co-design framework that leverages low tensor rankness towards energy-efficient high-accuracy DNN model and accelerators.
Biography
Dr. Bo Yuan is currently the assistant professor in the Department of Electrical and Computer Engineering in Rutgers University. Before that, he was with City University of New York from 2015-2018. Dr. Bo Yuan received his bachelor and master degrees from Nanjing University, China in 2007 and 2010, respectively. He received his PhD degree from University of Minnesota, Twin Cities in 2015. His research interests include algorithm and hardware co-design and implementation for machine learning and signal processing systems, error-resilient low-cost computing techniques for embedded and IoT systems and machine learning for domain-specific applications. He is the recipient of Global Research Competition Finalist Award in Broadcom Corporation. Dr. Yuan serves as technical committee track chair and technical committee member for several IEEE/ACM conferences. He is the associated editor of Springer Journal of Signal Processing System
Zoom Link: https://tamu.zoom.us/j/96343481647; Zoom ID: 963 4348 1647
CESG Seminar: Dr. Mayank Parasar
Friday, March 25, 2022
4:10 – 5:00 p.m.
ETB 1020 – *In-person* (Emerging Technologies Building)
Dr. Mayank Parasar
Samsung Austin R&D Center (SARC) in Austin, TX
Title: “Subactive Techniques for Guaranteeing Routing and Protocol Deadlock Freedom in Interconnection”
Talking Points:
-
- Correctness is of paramount concern in interconnection networks. (Routing and Protocol) Deadlock freedom is a cornerstone of correctness.
- Prior solutions either over-provision the network or incur performance penalty to provide deadlock freedom
- We propose new set of unified techniques to resolve routing and protocol deadlocks
Abstract
Interconnection networks are the communication backbone for any system. They occur at various scales: from on-chip networks, for example 2.5D/chiplet networks, between processing cores, to supercomputers between compute nodes, to data centers between high-end servers. One of the most fundamental challenges in an interconnection network is that of deadlocks. Deadlocks can be of two types: routing level deadlocks and protocol level deadlocks. Routing level deadlocks occur because of cyclic dependency between packets trying to acquire buffers, whereas protocol level deadlock occurs because the response message is stuck indefinitely behind the queue of request messages. Both kinds of deadlock render the forward movement of packets impossible leading to complete system failure.
Prior work either restricts the path that packets take in the network or provisions an extra set of buffers to resolve routing level deadlocks. For protocol level deadlocks, separate sets of buffers are reserved at every router for each message class. Naturally, proposed solutions either restrict the packet movement resulting in lower performance or require higher area and power.
We propose a new set of efficient techniques for providing both routing and protocol level deadlock freedom. Our techniques provide periodic forced movement to the packets in the network, which breaks any cyclic dependency of packets. Breaking this cyclic dependency results in resolving routing level deadlocks. Moreover, because of periodic forced movement, the response message is never stuck indefinitely behind the queue of request messages; therefore, our techniques also resolve protocol level deadlocks. We use the term ‘subactive’ for these new class of techniques.
Biography:
Dr. Mayank parasar works at Samsung Austin R&D Center (SARC) in Austin, TX. Mayank Parasar has received his Ph.D. from the School of Electrical and Computer Engineering at Georgia Institute of Technology. He received an M.S. in Electrical and Computer Engineering from Georgia Tech in 2017 and a B.Tech. in Electrical Engineering department from Indian Institute of Technology (IIT) Kharagpur in 2013.
He works in computer architecture with the research focus on proposing breakthrough solutions in the field of interconnection networks, memory system and system software/application layer co-design. His dissertation, titled Subactive Techniques for Guaranteeing Routing and Protocol Deadlock Freedom in Interconnection Networks, formulates techniques that guarantee deadlock freedom with a significant reduction in both area and power budget.
He held the position of AMD Student Ambassador at Georgia Tech in the year 2018-19. He received the Otto & Jenny Krauss Fellow award in the year 2015-16.
In-Person @ ETB 1020 @ 4:10 p.m. on Friday, 3/11/22