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CESG Seminar: Dr. Awais Altaf

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Thursday, June 2, 2022
10:00 – 10:50 a.m. (CST)
ETB 1035 – **In-person**

Dr. Muhammad Awais Bin Altaf
Assistant Professor, Electrical Engineering
Lahore University of Management Sciences (LUMS), Pakistan

Title: “On-Chip Energy-Efficient Neural Diagnostics: Advancing Neuroscience through Wearable Devices”

Talking Points:

  • Wearable Healthcare
  • On-Chip Energy Efficient Digital Processing Techniques for ML algorithms
  • Early Detection of Negative Emotion Outburst

Abstract
Artificial intelligence (AI) has influenced all aspects of human life and neurology is no exception to this growing trend. Today, neurology faces multiple challenges in the field of diagnostic and management modalities. This ranges from simple issues like identification of healthy sleep patterns to more complicated issues like early detection and reduction in the duration of rehabilitation of acute ischemic stroke diagnosis of rare subtypes of epilepsy. The increasing availability and progress of analytical techniques are opening new doors in health care. Machine learning, neural networks and other AI tools are used to classify the patient’s electroencephalogram (EEG) data to help neurologists in making an early diagnosis and improving care. Hence, the development of ultra-low-power System-on-Chip (SoC) for the next generation of the neuro-wearables, in the realms of detecting, diagnosing, and even preventing irreversible outcomes due to neurological disorders is essential. The uptake in the use of neuro-wearable technology by both patients and clinicians will have a huge impact on the future of healthcare.

This talk will cover the design strategies of energy-efficient patient-specific SoC biomedical devices. I will first explore the challenges, limitations and potential pitfalls in wearable interface circuit design, and strategies to overcome such issues. Moreover, I will describe on-chip energy-efficient digital processing techniques for the implementation of machine-learning algorithms for disease detection focusing on the negative emotion outburst early detection in Autistic patients. The talk will conclude with interesting aspects and opportunities that lie ahead.

Biography
Muhammad Awais Bin Altaf  (S’11–M’16) received a B.S. degree from the University of Engineering and Technology, Lahore, Pakistan, in 2008, and the M.Sc. and Ph.D. degrees in microsystems engineering and interdisciplinary engineering from the Masdar Institute of Science and Technology (MIST), Abu Dhabi, United Arab Emirates, in 2012 and 2016, respectively. From 2012 to 2013, he was a Digital Design Engineer Intern at Design Solutions, Global Foundries, Dresden, Germany, where he was involved in the implementation of digital test chips in support of 20 and 14 nm technologies. In 2015, he was an exchange-Ph.D. a student with the Massachusetts Institute of Technology, Cambridge, MA, USA.

During his stay at MIST, he developed an energy-efficient machine-learning-based feature extraction and classification processor as well as a SoC for epileptic seizure detection. He is the recipient of the IEEE Solid-State Circuits Society Predoctoral award for his work on efficient machine learning hardware implementation for wearable healthcare in 2016. Since 2016, he has been with the Electrical Engineering Department, Lahore University of Management Sciences (LUMS), Lahore, Pakistan where he is currently an Assistant Professor. His current research interests include analog and digital IC design, energy-efficient applied AI and the development of ultra-low-power circuits and systems for wearable bio-medical applications.

Google Scholar: https://scholar.google.ae/citations?user=XVyrDmgAAAAJ&hl=en

In-Person @ ETB 1035 @ 10:00 a.m. on Thursday, 6/2/22

Congratulations Spring 2022 Masters’ Graduates!

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CESG is proud to list our Spring 2022 graduating students. We celebrate these Masters students who are off to conquer their next goals in academia and industry!

Inimfon Idongesit Akpabio
Georges Alsankary
Suprith Balasubramanian
Ruilian Gao
Chia-Hang Lee
Hao Li
Kyler Ray Scott
Christopher P. Weber
Fangqing Xia
Chaoyang Zhu

May y’all have success and happiness in your futures and live by the Aggie Core Values!

Dr. P.R. Kumar – IEEE Alexander Graham Bell Medal

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Dr. Kumar is the 2022 recipient of one of the Institute of Electrical and Electronics Engineers’ (IEEE) most prestigious honors — the IEEE Alexander Graham Bell Medal. It is the highest award by IEEE in communications and networking. Kumar was recognized for his seminal contributions to the modeling, analysis and design of wireless networks.

For more, go to https://engineering.tamu.edu/news/2021/12/kumar-awarded-institute-of-electrical-and-electronics-engineers-medal.html.

Congratulations Dr. Kumar!

CESG Seminar: Dr. Bo Yuan

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Friday, January 25, 2021
4:10 – 5:00 p.m.
via Zoom (link below)
 
Dr. Bo Yuan
Asst. Professor, Dept. of Electrical & Computer Engineering, Rutgers University

Title: “Algorithm and Hardware Co-Design for Efficient Deep Learning: Sparse and Low-rank Perspective”

Talking Points

  • Algorithm and hardware co-design for structured and unstructured deep neural networks
  • Algorithm and hardware co-design for high-order tensor decomposition-based deep neural networks

Abstract
In the emerging artificial intelligence era, deep neural networks (DNNs), a.k.a. deep learning, have gained unprecedented success in various applications. However, DNNs are usually storage intensive, computation intensive and very energy consuming, thereby posing severe challenges on the future wide deployment in many application scenarios, especially for the resource-constraint low-power IoT application and embedded systems. In this talk, I will introduce the algorithm/hardware co-design works for energy-efficient DNN in my group, from both the sparse and low-rank perspectives. First, I will show the benefit of using structured and unstructured sparsity of DNN for designing low-latency and low-power DNN hardware accelerators. In the second part of my talk, I will present an algorithm/hardware co-design framework that leverages low tensor rankness towards energy-efficient high-accuracy DNN model and accelerators.

Biography
Dr. Bo Yuan is currently the assistant professor in the Department of Electrical and Computer Engineering in Rutgers University. Before that, he was with City University of New York from 2015-2018. Dr. Bo Yuan received his bachelor and master degrees from Nanjing University, China in 2007 and 2010, respectively. He received his PhD degree from University of Minnesota, Twin Cities in 2015. His research interests include algorithm and hardware co-design and implementation for machine learning and signal processing systems, error-resilient low-cost computing techniques for embedded and IoT systems and machine learning for domain-specific applications. He is the recipient of Global Research Competition Finalist Award in Broadcom Corporation. Dr. Yuan serves as technical committee track chair and technical committee member for several IEEE/ACM conferences. He is the associated editor of Springer Journal of Signal Processing System

Zoom Link: https://tamu.zoom.us/j/96343481647; Zoom ID: 963 4348 1647

CESG Seminar: Dr. Mayank Parasar

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Friday, March 25, 2022
4:10 – 5:00 p.m.
ETB 1020 – *In-person* (Emerging Technologies Building)
Dr. Mayank Parasar
Samsung Austin R&D Center (SARC) in Austin, TX

Title: “Subactive Techniques for Guaranteeing Routing and Protocol Deadlock Freedom in Interconnection”

Talking Points:

    • Correctness is of paramount concern in interconnection networks. (Routing and Protocol) Deadlock freedom is a cornerstone of correctness.
    • Prior solutions either over-provision the network or incur performance penalty to provide deadlock freedom
    • We propose new set of unified techniques to resolve routing and protocol deadlocks

Abstract
Interconnection networks are the communication backbone for any system. They occur at various scales: from on-chip networks, for example 2.5D/chiplet networks, between processing cores, to supercomputers between compute nodes, to data centers between high-end servers. One of the most fundamental challenges in an interconnection network is that of deadlocks. Deadlocks can be of two types: routing level deadlocks and protocol level deadlocks. Routing level deadlocks occur because of cyclic dependency between packets trying to acquire buffers, whereas protocol level deadlock occurs because the response message is stuck indefinitely behind the queue of request messages. Both kinds of deadlock render the forward movement of packets impossible leading to complete system failure.

Prior work either restricts the path that packets take in the network or provisions an extra set of buffers to resolve routing level deadlocks. For protocol level deadlocks, separate sets of buffers are reserved at every router for each message class. Naturally, proposed solutions either restrict the packet movement resulting in lower performance or require higher area and power.

We propose a new set of efficient techniques for providing both routing and protocol level deadlock freedom. Our techniques provide periodic forced movement to the packets in the network, which breaks any cyclic dependency of packets. Breaking this cyclic dependency results in resolving routing level deadlocks. Moreover, because of periodic forced movement, the response message is never stuck indefinitely behind the queue of request messages; therefore, our techniques also resolve protocol level deadlocks. We use the term ‘subactive’ for these new class of techniques.

Biography:
Dr. Mayank parasar works at Samsung Austin R&D Center (SARC) in Austin, TX. Mayank Parasar has received his Ph.D. from the School of Electrical and Computer Engineering at Georgia Institute of Technology. He received an M.S. in Electrical and Computer Engineering from Georgia Tech in 2017 and a B.Tech. in Electrical Engineering department from Indian Institute of Technology (IIT) Kharagpur in 2013.

He works in computer architecture with the research focus on proposing breakthrough solutions in the field of interconnection networks, memory system and system software/application layer co-design. His dissertation, titled Subactive Techniques for Guaranteeing Routing and Protocol Deadlock Freedom in Interconnection Networks, formulates techniques that guarantee deadlock freedom with a significant reduction in both area and power budget.

He held the position of AMD Student Ambassador at Georgia Tech in the year 2018-19. He received the Otto & Jenny Krauss Fellow award in the year 2015-16.

In-Person @ ETB 1020 @ 4:10 p.m. on Friday, 3/11/22