ECEN 468 Advanced Digital System Design

Spring 2018

Lecture: T/Th 8:00-9:15 a.m., Chem 255

Instructor: Jiang Hu, jianghu@tamu.edu, 979-847-8768 (office: 333L WEB)

Office hours: 2-3 p.m. Mondays; 10-11 a.m. Thursdays

Teaching assistant: Wenbin XU, wbxu@tamu.edu, lab webpage


Course Description
This course is mainly to provide students with a system perspective of chip design. System complexity growth is a fundamental technology trend that will continue for the foreseeable future. In this regard, SystemC is a very helpful means for electronic system level (ESL) design and transaction-level modeling. It is getting increasingly popular in chip design industry and likely to become de facto standard in future. The first half of this course and its labs are dedicated to learning and practicing how to use SystemC for hardware modeling. A simple image processing processor design is employed as the platform for the labs. In the second half of this course, this design is synthesized into logic level circuits through Verilog descriptions. Besides the system-level perspective, typical chip component designs, such as memory, bus, UART, are covered. This course also offers a taste of behavioral modeling of analog component (such as PLL) using Verilog-AMS.


Reference Books

  • “SystemC: From the Ground Up”, David C. Black, Jack Donovan, Bill Bunton, Anna Keist, Springer, 2nd Edition, 2009.
  • Online SystemC Tutorial.
  • TLM 2.0 Video Tutorial.
  • “Advanced Digital Design with the Verilog HDL”, Michael D. Ciletti, Prentice Hall, 2nd Edition, 2010.
  • “Modeling, Synthesis and Rapid Prototyping with the Verilog HDL”, Michael D. Ciletti, Prentice Hall, 1999.
  • The Designer’s Guide to Verilog-AMS.
  • “CMOS VLSI Design: a Circuits and Systems Perspective”, Neil H. E. Weste and David M. Harris, Addison-Wesley, 4th Edition, 2011.
  • “VLSI Digital Signal Processing Systems”, Keshab Parhi, John Wiley & Sons, Inc., 1999.

Lecture Agenda

  1. Introduction
  2. SystemC quick start
  3. SystemC concurrency
  4. SystemC processes
  5. UART
  6. SystemC channels and signals
  7. SystemC interfaces and ports
  8. Bus architecture
  9. SystemC dynamic processes and design hierarchy
  10. SystemC utilities and data types
  11. Edge detection algorithm
  12. Transaction-level modeling
  13. Design verification methodology
  14. RTL (Register Transfer Level) design
  15. Behavioral level design
  16. Logic design with Verilog
  17. Verilog data types
  18. Verilog simulation and testbench
  19. Verilog behavioral descriptions
  20. Verilog finite state machines
  21. Verilog synthesis of combinational logic
  22. Verilog synthesis of sequential logic
  23. Verilog operators
  24. Verilog delay models
  25. Verilog: synthesis of language constructs
  26. Verilog: user defined primitives
  27. Verilog: switch level models
  28. Basics of Verilog-AMS
  29. Mixed-signal models
  30. Phase-locked loops
  31. Chip I/O design
  32. High-speed links
  33. RTL optimization

Grading
Homework 10%
Midterm 1 20%
Midterm 2 20%
Lab 50%


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