Publications

Please be aware that all papers are copyrighted by the organization responsible for the corresponding conference or journal.


Book Chapters

  • J. Hu and S. S. Sapatnekar, “Non-Hanan optimization for global VLSI interconnect,” in Layout Optimization in VLSI Designs, B. Lu, D.-Z. Du and S. S. Sapatnekar, ed., Kluwer Academic Publishers, Boston, MA, pp. 89-123, 2002.
  • J. Hu, G. Robins and C. N. Sze, “Timing-driven interconnect synthesis,” in Handbook of Algorithms for Physical Design Automation, C. J. Alpert, D. P. Mehta and S. S. Sapatnekar, ed., Auerbach Publications, Taylor & Francis Group, Boca Raton, FL, pp. 509-534, 2009.
  • J. Hu, Z. Li and S. Hu, “Buffer insertion basics,” in Handbook of Algorithms for Physical Design Automation, C. J. Alpert, D. P. Mehta and S. S. Sapatnekar, ed., Auerbach Publications, Taylor & Francis Group, Boca Raton, FL, pp. 535-556, 2009.
  • J. Hu and C. N. Sze, “Buffering in the layout environment,” in Handbook of Algorithms for Physical Design Automation, C. J. Alpert, D. P. Mehta and S. S. Sapatnekar, ed., Auerbach Publications, Taylor & Francis Group, Boca Raton, FL, pp. 569-584, 2009.

Journal Articles

  1. H. Hou, J. Hu and S. S. Sapatnekar, “NonHanan routing,” IEEE Trans. Computer-Aided Design, Vol. 18, No. 4, pp. 436-444, April 1999.
  2. J. Hu and S. S. Sapatnekar, “Algorithms for non-Hanan-based optimization for VLSI interconnect under a higher order AWE model,” IEEE Trans. Computer-Aided Design, Vol. 19, No. 4, pp. 446-458, April 2000.
  3. C. J. Alpert, G. Gandham, J. Hu, J. L. Neves, S. T. Quay and S. S. Sapatnekar, “Steiner tree optimization for buffers, blockages and bays,” IEEE Trans. Computer-Aided Design, Vol. 20, No. 4, pp. 556-562, April 2001.
  4. J. Hu and S. S. Sapatnekar, “A survey on multi-net global routing for integrated circuits,” Integration: The VLSI Journal, Vol. 31, No. 1, pp. 1-49, November 2001. (Invited paper)
  5. C. J. Alpert, G. Gandham, M. Hrkic, J. Hu, A. B. Kahng, J. Lillis, B. Liu, S. T. Quay, S. S. Sapatnekar and A. J. Sullivan, “Buffered Steiner trees for difficult instances,” IEEE Trans. Computer-Aided Design, Vol. 21, No. 1, pp. 3-14, January 2002.
  6. J. Hu and S. S. Sapatnekar, “Performance driven global routing through gradual refinement,” The VLSI Design Journal, Vol. 15, No. 3, pp. 595-604, 2002.
  7. J. Hu and S. S. Sapatnekar, “A timing-constrained simultaneous global routing algorithm,” IEEE Trans. Computer-Aided Design, Vol. 21, No. 9, pp. 1025-1036, September 2002.
  8. J. Hu, C. J. Alpert, S. T. Quay and G. Gandham, “Buffer insertion with adaptive blockage avoidance”, IEEE Trans. Computer-Aided Design, Vol. 22, No. 4, pp. 492-498, April, 2003.
  9. C. J. Alpert, J. Hu, S. S. Sapatnekar and P. G. Villarrubia, “A practical methodology for early buffer and wire resource allocation,” IEEE Trans. Computer-Aided Design, Vol. 22, No. 5, pp. 573-583, May, 2003.
  10. C. J. Alpert, C. Chu, G. Gandham, M. Hrkic, J. Hu, C. Kashyap and S. T. Quay, “Simultaneous driver sizing and buffer insertion using a delay penalty estimation technique,” IEEE Trans. Computer-Aided Design, Vol. 23, No. 1, pp. 136-141, January, 2004.
  11. C. J. Alpert, G. Gandham, M. Hrkic, J. Hu, S. T. Quay and C. N. Sze, “Porosity-aware buffered Steiner tree construction,” IEEE Trans. Computer-Aided Design, Vol. 23, No. 4, pp. 517-526, April, 2004.
  12. H. Su, J. Hu, S. S. Sapatnekar and S. R. Nassif, “A methodology for the simultaneous design of supply and signal networks,” IEEE Trans. Computer-Aided Design, Vol. 23, No. 12, pp. 1614-1624, December, 2004.
  13. R. Chaturvedi and J. Hu, “An efficient merging scheme for prescribed skew clock routing,” IEEE Trans. VLSI Systems, Vol. 13, No. 6, pp. 750-754, June, 2005.
  14. Y. Lu, C. N. Sze, X. Hong, Q. Zhou, Y. Cai, L. Huang and J. Hu, “Navigating register placement for low power clock network design,” IEICE Transactions, Vol. E88-A, No. 12, pp. 3405-3411, December, 2005.
  15. D. Wu, J. Hu and R. Mahapatra, “Antenna avoidance in layer assignment,” IEEE Trans. Computer-Aided Design, Vol. 25, No. 4, pp. 734-748, April, 2006.
  16. C. J. Alpert, J. Hu, S. S. Sapatnekar and C.-N. Sze, “Accurate estimation of global buffer delay within a floorplan,” IEEE Trans. Computer-Aided Design, Vol. 25, No. 6, pp. 1140-1145, June, 2006.
  17. A. Rajaram, J. Hu and R. Mahapatra, “Reducing clock skew variability via cross links,” IEEE Trans. Computer-Aided Design, Vol. 25, No. 6, pp. 1176-1182, June, 2006.
  18. A. Rajaram, B. Lu, J. Hu, R. Mahapatra and W. Guo, “Analytical bound for unwanted clock skew due to wire width variation,” IEEE Trans. Computer-Aided Design, Vol. 25, No. 9, pp. 1869-1876, September, 2006.
  19. G. Venkataraman, J. Hu and F. Liu, “Integrated placement and skew optimization for rotary clocking,” IEEE Trans. VLSI Systems, Vol. 15, No. 2, pp. 149-158, February, 2007.
  20. B.-Y. Su, Y.-W. Chang and J. Hu, “An exact jumper insertion algorithm for antenna violation/fixing considering routing obstacles,” IEEE Trans. Computer-Aided Design, Vol. 26, No. 4, pp. 719-733, April, 2007.
  21. C.-N. Sze, C. J. Alpert, J. Hu and W. Shi, “Path based buffer insertion,” IEEE Trans. Computer-Aided Design, Vol. 26, No. 7, pp. 1346-1355, July, 2007.
  22. S. Hu, Q. Li, J. Hu and P. Li, “Utilizing redundancy for timing critical interconnect,” IEEE Trans. VLSI Systems, Vol. 15, No. 10, pp. 1067-1080, October, 2007.
  23. S. Hu, C. J. Alpert, J. Hu, S. Karandikar, Z. Li, W. Shi and C. N. Sze, “Fast algorithms for slew constrained minimum cost buffering,” IEEE Trans. Computer-Aided Design, Vol. 26, No. 11, pp. 2009-2022, November, 2007.
  24. K. Cao, J. Hu and M. Cheng, “Wire sizing and spacing for lithographic printability and timing optimization,” IEEE Trans. VLSI Systems, Vol. 15, No. 12, pp. 1332-1340, December, 2007.
  25. K. Cao and J. Hu, “ASIC design flow considering lithography-induced effects,” IET Circuits, Devices and Systems, Vol. 2, No. 1, pp. 23-29, February, 2008.
  26. C. Zhuo, J. Hu, M. Zhao and K. Chen, “Power grid analysis and optimization using algebraic multigrid,” IEEE Trans. Computer-Aided Design, Vol. 27, No. 4, pp. 738-751, April, 2008.
  27. W. Shen, Y. Cai, X. Hong, J. Hu and B. Lu, “Zero skew clock routing in X-architecture based on an improved greedy matching algorithm,” Integration, the VLSI Journal, Vol. 41, No. 3, pp. 426-438, May, 2008.
  28. U. Padmanabhan, J. M. Wang and J. Hu, “Robust clock tree routing in the presence of process variations,” IEEE Trans. Computer-Aided Design, Vol. 27, No. 8, pp. 1385-1397, August, 2008.
  29. Y. Liu, J. Hu and W. Shi, “Buffering interconnect for multicore processor designs,” IEEE Trans. Computer-Aided Design, Vol. 27, No. 12, pp. 2183-2196, December, 2008.
  30. Y. Liu, T. Zhang and J. Hu, “Design of voltage overscaled low-power Trellis decoders in presence of process variations,” IEEE Trans. VLSI Systems, Vol. 17, No. 3, pp. 439-443, March, 2009.
  31. S. Hu, M. Ketkar and J. Hu, “Gate sizing for cell-library-based designs,” IEEE Trans. Computer-Aided Design, Vol. 28, No. 6, pp. 818-825, June, 2009.
  32. R. Samanta, G. Venkataraman and J. Hu, “Clock buffer polarity assignment for power noise reduction,” IEEE Trans. VLSI Systems, Vol. 17, No. 6, pp. 770-780, June, 2009.
  33. G. Venkataraman, Z. Feng, J. Hu and P. Li, “Combinatorial algorithms for fast clock mesh optimization,” IEEE Trans. VLSI Systems, Vol. 18, No. 1, pp. 131-141, January, 2010.
  34. Y. Liu and J. Hu, “A new algorithm for simultaneous gate sizing and threshold voltage assignment,” IEEE Trans. Computer-Aided Design, Vol. 29, No. 2, pp. 223-234, February, 2010.
  35. S. Hu, P. Shah and J. Hu, “Pattern sensitive placement perturbation for manufacturability,” IEEE Trans. VLSI Systems, Vol. 18, No. 6, pp. 1002-1006, June, 2010.
  36. R. Samanta, J. Hu and P. Li, “Discrete buffer and wire sizing for link-based non-tree clock networks,” IEEE Trans. VLSI Systems, Vol. 18, No. 7, pp. 1025-1035, July, 2010.
  37. X. Ye, P. Li, M. Zhao, R. Panda and J. Hu, “Scalable analysis of mesh-based clock distribution networks using application-specific reduced order modeling,” IEEE Trans. Computer-Aided Design, Vol. 29, No. 9, pp. 1342-1353, September, 2010.
  38. W. Shen, Y. Cai, X. Hong and J. Hu, “An effective gated clock tree design based on activity and register aware placement,” IEEE Trans. VLSI Systems, Vol. 18, No. 12, pp. 1639-1648, December, 2010.
  39. M. A. R. Chaudhry, Z. Asad, A. Sprintson and J. Hu, “Efficient congestion mitigation using congestion-aware Steiner trees and network coding topologies,” VLSI Design Journal, Vol. 2011, January, 2011.
  40. Y. Liu, R. Shelar and J. Hu, “Simultaneous technology mapping and placement for delay minimization,” IEEE Trans. Computer-Aided Design, Vol. 30, No. 3, pp. 416-426, March 2011.
  41. Y. Liu and J. Hu, “GPU-based parallelization for fast circuit optimization,” ACM Trans. Design Automation of Electronic Systems, Vol. 16, No. 3, pp. 24:1-14, June 2011.
  42. M. Ozdal, S. Burns and J. Hu, “Algorithms for gate sizing and device parameter selection for high-performance designs,” IEEE Trans. Computer-Aided Design, Vol. 31, No. 10, pp. 1558-1571, October, 2012.
  43. X. Chen, J. Hu and N. Xu, “Regularity-constrained floorplanning for multi-core processors,” Integration: the VLSI Journal, Vol. 47, No. 1, pp. 86-95, January 2013.
  44. K.-N. Shim, J. Hu and J. Silva-Martinez, “Dual-level adaptive supply voltage system for variation resilience,” IEEE Trans. VLSI Systems, Vol.21, No. 6, pp. 1041-1052, June 2013.
  45. K.-N. Shim and J. Hu, “Boostable repeater design for variation resilience in VLSI interconnects,” IEEE Trans. VLSI Systems, Vol. 21, No. 9, pp. 1619-1631, September 2013.
  46. X. Chen, Z. Xu, H. Kim, P. Gratz, J. Hu, M. Kishinevsky and U. Ogras, “In-network monitoring and control policy for DVFS of CMP networks-on-chip and last level caches,”ACM Trans. Design Automation of Electronic Systems, Vol. 18, No. 4, October 2013.
  47. J.-Y. Won, H. Ryu, T. Debruck, J. Lee and J. Hu, “Proximity sensing based on dynamic vision sensor for mobile devices,” IEEE Trans. Industrial Electronics, Vol. 62, No. 1, pp. 536-544, July 2014.
  48. J.-Y. Won, P. Gratz, S. Shakkottai and J. Hu, “Resource sharing centric dynamic voltage and frequency scaling for CMP cores, uncore, and memory,” ACM Trans. Design Automation of Electronic Systems, Vol. 21, No. 4, May 2016.

Conference Papers

  1. J. Hu and S. S. Sapatnekar, “Simultaneous buffer insertion and non-Hanan optimization for VLSI interconnect under a higher order AWE model,” Proc. ACM International Symposium on Physical Design, pp. 133-138, 1999.
  2. J. Hu and S. S. Sapatnekar, “FAR-DS: Full-plane AWE Routing with Driver Sizing”, Proc. ACM/IEEE Design Automation Conference, pp. 84-89, 1999.
  3. J. Hu and S. S. Sapatnekar, “A timing-constrained algorithm for simultaneous global routing of multiple nets,” Proc. IEEE/ACM International Conference on Computer-Aided Design, pp. 99-103, 2000.
  4. C. J. Alpert, G. Gandham, M. Hrkic, J. Hu, A. B. Kahng, J. Lillis, B. Liu, S. T. Quay, S. S. Sapatnekar, A. J. Sullivan and P. G. Villarrubia, “Buffered Steiner trees for difficult instances,”Proc. ACM International Symposium on Physical Design, pp. 4-9, 2001.
  5. C. J. Alpert, G. Gandham, J. Hu, J. L. Neves, S. T. Quay and S. S. Sapatnekar, “Steiner tree optimization for buffers, blockages and bays,” Proc. IEEE International Symposium on Circuits and Systems, pp. 399-402, 2001.
  6. C. J. Alpert, J. Hu, S. S. Sapatnekar and P. G. Villarrubia, “A practical methodology for early buffer and wire resource allocation,” Proc. ACM/IEEE Design Automation Conference, pp. 189-194, 2001. (Best Paper Award)
  7. J. Hu and S. S. Sapatnekar, “Performance driven global routing through gradual refinement,” Proc. IEEE International Conference on Computer Design, pp. 481-483, 2001.
  8. J. Hu, C. J. Alpert, S. T. Quay and G. Gandham, “Buffer insertion with adaptive blockage avoidance,” Proc. ACM International Symposium on Physical Design, pp. 92-97, 2002.
  9. C. J. Alpert, C. Chu, G. Gandham, M. Hrkic, J. Hu, C. Kashyap and S. T. Quay, “Simultaneous driver sizing and buffer insertion using a delay penalty estimation technique,” Proc. ACM International Symposium on Physical Design, pp. 104-109, 2002.
  10. H. Su, J. Hu, S. S. Sapatnekar and S. Nassif, “Congestion-driven codesign of power and signal networks,” Proc. ACM/IEEE Design Automation Conference, pp. 64-69, 2002.
  11. C. J. Alpert, G. Gandham, M. Hrkic, J. Hu and S. T. Quay, “Porosity aware buffered Steiner tree construction,” Proc. ACM International Symposium on Physical Design, pp. 158-165, 2003.
  12. B. Lu, J. Hu, G. Ellis and H. Su, “Process variation aware clock tree routing,” Proc. ACM International Symposium on Physical Design, pp. 174-181, 2003.
  13. R. Chaturvedi and J. Hu, “A simple yet effective merging scheme for prescribed-skew clock routing,” Proc. IEEE International Conference on Computer Design, pp. 282-287, 2003.
  14. A. Rajaram, B. Lu, W. Guo, R. Mahapatra and J. Hu, “Analytical bound for unwanted clock skew due to wire width variation,” Proc. IEEE/ACM International Conference on Computer-Aided Design, pp. 401-406, 2003.
  15. C. N. Sze, J. Hu and C. J. Alpert, “Place and route aware buffered Steiner tree construction,” Proc. Asia and South Pacific Design Automation Conference, pp. 355- 360, 2004. (Best Paper Nominee)
  16. D. Wu, J. Hu, R. Mahapatra and M. Zhao, “Layer assignment for crosstalk risk minimization,” Proc. Asia and South Pacific Design Automation Conference, pp. 159-162, 2004.
  17. K. Cao, J. Hu and M. Cheng, “Layout modification for library cell Alt-PSM composability,” Proc. SPIE, Vol. 5379, pp. 253-259, 2004.
  18. R. Chaturvedi and J. Hu, “Buffered clock tree for high quality IC designs,” Proc. IEEE International Symposium on Quality Electronic Design, pp. 381-386, 2004.
  19. A. Rajaram, J. Hu and R. Mahapatra, “Reducing clock skew variability via cross links,” Proc. ACM/IEEE Design Automation Conference, pp. 18-23, 2004. (Best Paper Nominee)
  20. C. J. Alpert, M. Hrkic, J. Hu and S. T. Quay, “Fast and flexible buffer trees that navigate the physical layout environment,” Proc. ACM/IEEE Design Automation Conference, pp. 24-29, 2004.
  21. C. J. Alpert, J. Hu, S. S. Sapatnekar and C.-N. Sze, “Accurate estimation of global buffer delay within a floorplan,” Proc. IEEE/ACM International Conference on Computer-Aided Design, pp. 706-711, 2004.
  22. V. Seth, M. Zhao and J. Hu, “Exploiting level sensitive latches in wire pipelining,” Proc. IEEE/ACM International Conference on Computer-Aided Design, pp. 283-290, 2004.
  23. Z. Li, C.-N. Sze, C. J. Alpert, J. Hu and W. Shi, “Making fast buffer insertion even faster via approximation techniques,” Proc. Asia and South Pacific Design Automation Conference, pp. 13-18, 2005.
  24. K. Cao, P. Dhawan and J. Hu, “Library cell layout with Alt-PSM compliance and composability,” Proc. Asia and South Pacific Design Automation Conference, pp. 216-219, 2005.
  25. D. Wu, J. Hu, M. Zhao and R. Mahapatra, “Timing driven track routing considering coupling capacitance,” Proc. Asia and South Pacific Design Automation Conference, pp. 1156-1159, 2005.
  26. G. Venkataraman, C.-N. Sze and J. Hu, “Skew scheduling and clock routing for improved tolerance to process variations,” Proc. Asia and South Pacific Design Automation Conference, pp. 594-599, 2005.
  27. L. Huang, Y. Cai, Q. Zhou, X. Hong, J. Hu and Y. Lu, “Clock network minimization methodology based on incremental placement,” Proc. Asia and South Pacific Design Automation Conference, pp. 99-102, 2005.
  28. Y. Lu, C.-N. Sze, X. Hong, Q. Zhou, Y. Cai, L. Huang and J. Hu, “Register placement for low power clock network,” Proc. Asia and South Pacific Design Automation Conference, pp. 588-593, 2005.
  29. D. Wu, J. Hu and R. Mahapatra, “Coupling aware timing optimization and antenna avoidance in layer assignment,” Proc. ACM International Symposium on Physical Design, pp. 20-27, 2005.
  30. A. Rajaram, D. Pan and J. Hu, “Improved algorithms for link based non-tree clock network for skew variability reduction,” Proc. ACM International Symposium on Physical Design, pp. 55-62, 2005.
  31. Y. Lu, C.-N. Sze, X. Hong, Q. Zhou, Y. Cai, L. Huang and J. Hu, “Navigating registers in placement for clock network minimization,” Proc. ACM/IEEE Design Automation Conference, pp. 176-181, 2005.
  32. C.-N. Sze, C. J. Alpert, J. Hu and W. Shi, “Path based buffer insertion,” Proc. ACM/IEEE Design Automation Conference, pp. 509-514, 2005.
  33. D. Wu, G. Venkataraman, J. Hu, Q. Li and R. Mahapatra, “DiCER: Distributed and Cost-Effective Redundancy for variation tolerance,” Proc. IEEE/ACM International Conference on Computer-Aided Design, pp. 393-397, 2005.
  34. G. Venkataraman, N. Jayakumar, J. Hu, P. Li, S. Khatri, A. Rajaram, P. McGuinness and C. J. Alpert, “Practical techniques to reduce skew and its variations in buffered clock networks,”Proc. IEEE/ACM International Conference on Computer-Aided Design, pp. 592-596, 2005.
  35. G. Venkataraman, J. Hu, F. Liu and C. N. Sze, “Integrated placement and skew optimization for rotary clocking,” Proc. ACM/IEEE Design Automation and Test in Europe, pp. 756-761, 2006.
  36. M.-S. Kim and J. Hu, “Associative skew clock routing for difficult instances,” Proc. ACM/IEEE Design Automation and Test in Europe, pp. 762-767, 2006.
  37. C. Zhuo, J. Hu and K. Chen, “An improved AMG-based method for fast power grid analysis,” Proc. IEEE International Symposium on Quality Electronic Design, pp. 290-295, 2006.
  38. Z. Feng, P. Li and J. Hu, “Efficient model update for general link-insertion networks,” Proc. IEEE International Symposium on Quality Electronic Design, pp. 43-50, 2006.
  39. U. Padmanabhan, J. M. Wang and J. Hu, “Statistical clock tree routing for robustness to process variations,” Proc. ACM International Symposium on Physical Design, pp. 149-156, 2006.
  40. B.-Y. Su, Y.-W. Chang and J. Hu, “An optimal jumper insertion algorithm for antenna effect avoidance/fixing on general routing trees with obstacles,” Proc. ACM International Symposium on Physical Design, pp. 56-63, 2006.
  41. W. Shen, Y. Cai, J. Hu, X. Hong and B. Lu, “High performance clock routing in X-architecture,” Proc. IEEE International Symposium on Circuits and Systems, pp. 2081-2084, 2006.
  42. S. Hu, Q. Li, J. Hu and P. Li, “Steiner network construction for timing critical nets,” Proc. ACM/IEEE Design Automation Conference, pp. 379-384, 2006.
  43. S. Hu, C. J. Alpert, J. Hu, S. Karandikar, Z. Li, W. Shi and C. N. Sze, “Fast algorithms for slew constrained minimum cost buffering,” Proc. ACM/IEEE Design Automation Conference, pp. 308-313, 2006.
  44. K. Cao, S. Dobre and J. Hu, “Standard cell characterization considering lithography induced variations,” Proc. ACM/IEEE Design Automation Conference, pp. 801-804, 2006.
  45. R. Samanta, G. Venkataraman and J. Hu, “Clock buffer polarity assignment for power noise reduction,” IEEE/ACM International Conference on Computer-Aided Design, pp.558-562, 2006.
  46. G. Venkataraman, Z. Feng, J. Hu and P. Li, “Combinatorial algorithms for fast clock mesh optimization,” IEEE/ACM International Conference on Computer-Aided Design, pp. 563-567, 2006.
  47. Z. Jiang, S. Hu, J. Hu, Z. Li and W. Shi, “A new RLC buffer insertion algorithm,” IEEE/ACM International Conference on Computer-Aided Design, pp. 553-557, 2006.
  48. C. Zhuo, J. Hu, M. Zhao and K. Chen, “Fast decap allocation method based on algebraic multigrid,” IEEE/ACM International Conference on Computer-Aided Design, pp. 107-111, 2006.
  49. G. Venkataraman, J. Hu, “A placement methodology for robust clocking,” International Conference on VLSI Design, pp. 881-886, 2007.
  50. B. Liu, A. B. Kahng, X. Xu, J. Hu and G. Venkataraman, “A global minimum clock distribution network augmentation algorithm for guaranteed clock skew yield,” Asia and South Pacific Design Automation Conference, pp. 24-31, 2007.
  51. K. Cao, J. Hu and M. Cheng, “Wire sizing and spacing for lithographic printability optimization,” SPIE Advanced Lithography, pp. 652111:1-9, 2007.
  52. S. Hu and J. Hu, “Pattern sensitive placement for manufacturability,” ACM International Symposium on Physical Design, pp. 27-34, 2007.
  53. Z. Jiang, S. Hu, J. Hu and W. Shi, “An efficient algorithm for RLC buffer insertion,” IEEE International Symposium on Quality Electronic Design, pp. 171-175, 2007.
  54. W. Shen, Y. Cai, X. Hong, J. Hu and B. Lu, “Planar-CRX: a single-layer zero skew clock routing in X-architecture,” IEEE International Symposium on Quality Electronic Design, pp. 299-304, 2007.
  55. Y. Liu, T. Zhang and J. Hu, “Soft clock skew scheduling for system-level variation tolerance in digital signal processing circuits,” IEEE International Symposium on Quality Electronic Design, pp. 749-754, 2007.
  56. W. Shen, Y. Cai, X. Hong and J. Hu, “Activity-aware register placement for low power gated clock tree construction,” IEEE Computer Society Annual Symposium on VLSI, pp. 383-388, 2007.
  57. S. Hu, M. Ketkar and J. Hu, “Gate sizing for cell library based designs,” ACM/IEEE Design Automation Conference, pp. 847-852, 2007.
  58. S. Hu and J. Hu, “Unified adaptivity optimization of clock and logic signals,” IEEE/ACM International Conference on Computer-Aided Design, pp. 125-130, 2007.
  59. C. Zhuo, H. Zhang, R. Samanta, J. Hu and K. Chen, “Modeling, optimization and control of rotary traveling-wave oscillator,” IEEE/ACM International Conference on Computer-Aided Design, pp. 476-480, 2007.
  60. X. Ye, P. Li, M. Zhao, R. Panda and J. Hu, “Analysis of large clock meshes via harmonic-weighted model order reduction and port sliding,” IEEE/ACM International Conference on Computer-Aided Design, pp. 627-631, 2007.
  61. S. Hu and J. Hu, “A new fast slew buffering algorithm without input slew assumptions,” IEEE Dallas Circuits and Systems Workshop on System-on-Chip, pp. 1-4, 2007.
  62. Y. Wang, Q. Zhou, Y. Cai, J. Hu and X. Hong, “Low power clock buffer planning methodology in FD placement for large scale circuit design,” Asia and South Pacific Design Automation Conference, pp. 370-375, 2008.
  63. S. Varadan, J. M. Wang and J. Hu, “Handling partial correlations in yield prediction,” Asia and South Pacific Design Automation Conference, pp. 543-548, 2008.
  64. R. Samanta, G. Venkataraman, N. Shah and J. Hu, “Elastic timing scheme for energy-efficient and robust performance,” IEEE International Symposium on Quality Electronic Design, pp. 537-542, 2008.
  65. X. Ye, M. Zhao, R. Panda, P. Li and J. Hu, “Accelerating clock mesh simulation using matrix-level macromodels and dynamic time step rounding,” IEEE International Symposium on Quality Electronic Design, pp. 627-632, 2008.
  66. Y. Liu, J. Hu and W. Shi, “Multi-scenario buffer insertion in multi-core processor designs,” ACM International Symposium on Physical Design, pp. 15-22, 2008.
  67. R. Samanta, J. Hu and P. Li, “Discrete buffer and wire sizing for link-based non-tree clock networks,” ACM International Symposium on Physical Design, pp. 175-181, 2008.
  68. W. Shen, Y. Cai, X. Hong and J. Hu, “Activity and register placement aware gated clock network design,” ACM International Symposium on Physical Design, pp. 182-189, 2008.
  69. N. Shah, R. Samanta, M. Zhang, J. Hu and D. Walker, “Built-in proactive tuning system for circuit aging resilience,” IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, pp. 96-104, 2008.
  70. W. Shen, Y. Cai, X. Hong and J. Hu, “Gate planning during placement for gated clock network,” IEEE International Conference on Computer Design, pp. 128-133, 2008.
  71. Y. Liu, R. Shelar and J. Hu, “Delay-optimal simultaneous technology mapping and placement with applications to timing optimization,” IEEE/ACM International Conference on Computer-Aided Design, pp. 101-106, 2008.
  72. Y. Liu and J. Hu, “A new algorithm for simultaneous gate sizing and threshold voltage assignment,” ACM International Symposium on Physical Design, pp. 27-34, 2009. (Best Paper Nominee)
  73. P. Shah and J. Hu, “Impact of lithography-friendly circuit layout,” ACM/IEEE Great Lakes Symposium on VLSI, pp. 385-388, 2009.
  74. M. A. R. Chaudhry, Z. Asad, A. Sprintson and J. Hu, “Efficient rerouting algorithms for congestion mitigation,” IEEE Computer Society Annual Symposium on VLSI, pp. 43-48, 2009.
  75. N. Nemade, A. Sprintson and J. Hu, “Applications of network coding in global routing,” IEEE International Conference on IC Design and Technology, pp. 55-58, 2009.
  76. Y. Liu and J. Hu, “GPU-based parallelization for fast circuit optimization,” ACM/IEEE Design Automation Conference, pp. 943-946, 2009.
  77. S. Prabhu, B. Grot, P. V. Gratz and J. Hu, “Ocin-tsim: DVFS aware simulator for NoCs,” Workshop on SoC Architecture, Accelerators and Workloads, 2010.
  78. Y. Wei, J. Hu, F. Liu and S. Sapatnekar, “Physical design techniques for optimizing RTA-induced variations,” Asia and South Pacific Design Automation Conference, pp. 745-750, 2010.
  79. F. Yang, Y. Cai, Q. Zhou and J. Hu, “SAT based multi-net rip-up-and-reroute for manufacturing hotspot removal,” Design Automation and Test in Europe, pp. 1369-1372, 2010.
  80. K.-N. Shim, J. Hu and J. Silva-Martinez, “A dual-level adaptive supply voltage system for variation resilience,” IEEE International Symposium on Quality Electronic Design, pp. 38-43, 2010.
  81. V. R. Mekala, Y. Liu, X. Ye, P. Li and J. Hu, “Accurate clock mesh sizing via sequential quadratic programming,” ACM International Symposium on Physical Design, pp. 135-142, 2010.
  82. T. Jindal, C. J. Alpert, J. Hu, Z. Li, G.-J. Nam and C. B. Winn, “Detecting tangled logic structures in VLSI netlists,” ACM/IEEE Design Automation Conference, pp. 603-608, 2010.
  83. Y. Liu, Y. Yang and J. Hu, “Clustering-based simultaneous task and voltage scheduling for NOC systems,” IEEE/ACM International Conference on Computer-Aided Design, pp. 277-283, 2010.
  84. K.-N. Shim and J. Hu, “Transient and fine-grained voltage adaptation for variation resilience in VLSI interconnects,” IEEE International Symposium on Quality Electronic Design, pp. 80-86, 2011.
  85. Y.-L. Huang, J. Hu and W. Shi, “Lagrangian relaxation for gate implementation selection,” ACM International Symposium on Physical Design, pp. 167-174, 2011.
  86. X. Chen, J. Hu and N. Xu, “Regularity-constrained floorplanning for multi-core processors,” ACM International Symposium on Physical Design, pp. 99-105, 2011.
  87. M. Ozdal, S. Burns and J. Hu, “Gate sizing and device technology selection algorithms for high-performance industrial designs,” IEEE/ACM International Conference on Computer-Aided Design, pp. 724-731, 2011. (Best Paper Award)
  88. X. Chen, Z. Xu, H. Kim, P. Gratz, J. Hu, M. Kishinevsky and U. Ogras, “In-network monitoring and control policy for DVFS of CMP networks-on-chip and last level caches,” IEEE/ACM International Symposium on Networks-on-Chip, pp. 43-50, 2012. (Best Paper Nominee)
  89. Q. Zhao and J. Hu, “Track assignment considering crosstalk-induced performance degradation,” IEEE International Conference on Computer Design, pp. 506-507, 2012.
  90. K.-N. Shim and J. Hu, “A low overhead built-in delay testing with voltage and frequency adaptation for variation resilience,” IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, pp. 170-177, 2012.
  91. X. Chen, Z. Xu, H. Kim, P. Gratz, J. Hu, M. Kishinevsky, U. Ogras and R. Ayoub, “Dynamic voltage and frequency scaling for shared resources in multicore processor designs,” ACM/IEEE Design Automation Conference, 2013.
  92. D. Kadjo, H. Kim, P. Gratz, J. Hu and R. Ayoub, “Power gating with block migration in chip-multiprocessor last-level caches,” IEEE International Conference on Computer Design, pp. 93-99, 2013.
  93. G. Yang, H. He and J. Hu, “Resource allocation algorithms for guaranteed service in application-specific NoCs,” IEEE International Conference on Computer Design, pp. 483-486, 2013.
  94. J.-Y. Won, X. Chen, P. Gratz, J. Hu and V. Soteriou, “Up by their bootstraps: online learning in artificial neural networks for CMP uncore power management,” IEEE International Symposium on High Performance Computer Architecture, pp. 308-319, 2014. (HiPEAC Paper Award)
  95. A. Singh and J. Hu, “Low power and variation tolerant design using planar asymmetric double gate transistor,” IEEE International Midwest Symposium on Circuits and Systems, pp. 1021-1024, 2014.
  96. H. He, G. Yang and J. Hu, “Algorithms for power-efficient QoS in application specific NoCs,” ACM/IEEE International Symposium on Low Power Electronics and Design, pp. 165-170, 2014.
  97. S. Rasheed, P. Gratz, S. Shakkottai and J. Hu, “STORM: a Simple Traffic-Optimized Router Microarchitecture for networks-on-chip,” IEEE/ACM International Symposium on Networks-on-Chip, pp. 176-177, 2014.
  98. R. Kumar, B. Li, Y. Shen, U. Schlichtmann and J. Hu, “Timing Verification for Adaptive Integrated Circuits,” ACM/IEEE Design Automation and Test in Europe, pp. 1587-1590, 2015.
  99. C. Li, W. Luo, S. Sapatnekar and J. Hu, “Joint Precision Optimization and High Level Synthesis for Approximate Computing,” ACM/IEEE Design Automation Conference, 2015.
  100. J. Wang, C. Shi, E. Sanchez-Sinencio and J. Hu, “Built-In Self Optimization for Variation Resilience of Analog Filters,” IEEE Computer Society Annual Symposium on VLSI, pp. 656-661, 2015.
  101. H. He, J. Wang and J. Hu, “Collaborative Gate Implementation Selection and Adaptivity Assignment for Robust Combinational Circuits,” ACM/IEEE International Symposium on Low Power Electronics and Design, pp. 122-127, 2015.
  102. J.-Y. Won, P.V. Gratz, S. Shakkottai and J. Hu, “Having Your Cake and Eating It Too: Energy Savings without Performance Loss Through Resource Sharing Driven Power Management,”ACM/IEEE International Symposium on Low Power Electronics and Design, pp. 255-260, 2015.
  103. C.-Y. Wu, H. Graeb and J. Hu, “A Pre-search Assisted ILP Approach to Analog Integrated Circuit Routing,” IEEE International Conference on Computer Design, pp. 244-250, 2015.
  104. Y. Shen and J. Hu, “GPU Acceleration for PCA-Based Statistical Static Timing Analysis,” IEEE International Conference on Computer Design, pp. 674-679, 2015.
  105. H. Zhou, J. Hu, S. Khatri, F. Liu, C. C.-N. Sze and M. R. Yousefi, “GPU Acceleration for Bayesian Control of Markovian Genetic Regulatory Networks,” IEEE International Conference on Biomedical and Health Informatics, 2016.
  106. A. Lu, H. He and J. Hu, “Proximity Optimization for Adaptive Circuit Design,” ACM International Symposium on Physical Design, 2016.
  107. Y. Wang, P. Chen, J. Hu and J. Rajendran, “The Cat and Mouse in Split Manufacturing,” ACM/IEEE Design Automation Conference, 2016.
  108. F. S. Snigdha, D. Sengupta, J. Hu and S. S. Sapatnekar, “Optimal Design of JPEG Hardware under the Approximate Computing Paradigm,” ACM/IEEE Design Automation Conference, 2016.
  109. C. Li, S. S. Sapatnekar and J. Hu, “Control Synthesis and Delay Sensor Deployment for Efficient ASV Designs,” IEEE/ACM International Conference on Computer-Aided Design, 2016.
  110. Y. Wang, P. Chen, J. Hu and J. Rajendran, “Routing Perturbation for Enhanced Security in Split Manufacturing,” Asia and South Pacific Design Automation Conference, 2017.
  111. H. He, J. Hu and D. Da Silva, “Enhancing Datacenter Resource Management through Temporal Logic Constraints,” IEEE International Parallel and Distributed Processing Symposium, 2017.
  112. D. Sengupta, F. S. Snigdha, J. Hu and S. S. Sapatnekar, “SABER: Selection of Approximate Bits for the Design of Error Tolerant Circuits,” ACM/IEEE Design Automation Conference, 2017.
  113. W. Xu, S. S. Sapatnekar and J. Hu, “A Simple Yet Efficient Accuracy Configurable Adder Design,” ACM/IEEE International Symposium on Low Power Electronics and Design, 2017.
  114. L. Sun, Y. Liu, L. Liu, J. Hu and S. Hu, “A Comparative Study on Neural Network-Based Prediction of Smart Community Energy Consumption,” IEEE Smart World Congress, 2017.
  115. H. Zhou, S. Khatri, J. Hu, F. Liu and C. Sze, “Fast and Highly Scalable Bayesian MDP on a GPU Platform,” ACM Conference on Bioinformatics, Computational Biology, and Health Informatics, 2017.
  116. J. Wang, C. Shi, A. Sanabria-Borbon, E. Sanchez-Sinencio and J. Hu, “Thwarting Analog IC Piracy via Combinational Locking,” IEEE International Test Conference, 2017.
  117. L. Feng, Y. Wang, W.-K. Mak, J. Rajendran and J. Hu, “Making Split Fabrication Synergistically Secure and Manufacturable,” IEEE/ACM International Conference on Computer-Aided Design, 2017. (Best Paper Nominee)
  118. Y. Wang, T. Cao, J. Hu and J. Rajendran, “Front-End-of-Line Attacks in Split Manufacturing,” IEEE/ACM International Conference on Computer-Aided Design, 2017.
  119. L. Sun, Y. Yang, J. Hu, D. Porter, T. Marek and C. Hillyer, “Reinforcement Learning Control for Water-Efficient Agricultural Irrigation,” IEEE International Conference on Ubiquitous Computing and Communications, 2017.
  120. Y. Yang, L. Sun, J. Hu, D. Porter, T. Marek and C. Hillyer, “A Reliable Soil Moisture Sensing Methodology for Agricultural Irrigation,” IEEE International Conference on Ubiquitous Computing and Communications, 2017.

Tutorial C. J. Alpert, J. Hu, N. Menezes and W. Shi, “Buffering interconnect: from basics to breakthroughs,” ACM/IEEE Design Automation Conference, San Diego, 2004.

Software Release
Statistical timing analysis with GPU acceleration, 2016.
Network flow attack tool in split manufacturing, 2017.