Publications

Patents

  1. J. Rajendran, O. Sinanoglu and R. Karri, System, Method And Computer-Accessible Medium For Fault Analysis Driven Selection Of Logic Gates To Be Camouflaged, U.S. Patent pending, filed Sep 2013.
  2. J. Rajendran, Y. Pino, R. Karri and O. Sinanoglu, System, Method and Computer-Accessible Medium for Facilitating An Unbreakable Logic Encryption, U.S. Patent pending, filed Mar, 2013.
  3. J. Rajendran, O. Sinanoglu and R. Karri, System, Method and Computer-Accessible Medium for Providing Secure Split Manufacturing, U.S. Patent pending, filed Mar, 2013.
  4. J. Rajendran, Y. Pino, O. Sinanoglu, and R. Karri, Systems, processes, and computer-accessible medium for providing Logic Encryption using Fault analysis, U.S. Patent pending, filed Jan, 2012.
  5. V. Jyothi, R. Karri, J. Rajendran, and O. Sinanoglu, Reconfiguring functional path into Trojan detecting Ring oscillators, U.S. Patent pending, filed March, 2011.

Book Chapters

  1. R. Karri, J. Rajendran, and K. Rosenfeld, Trojan Taxonomy, a book chapter in Hardware Security and Trust, Pages 325-338, 2012.

Journals

  1. Yujie Wang, Pu Chen, Jiang Hu, Guofeng Li, Jeyavijayan Rajendran, “The Cat and Mouse in Split Manufacturing,” IEEE Transactions on VLSI Systems, Volume 26, Issue 5, Pages: 805-817, 2018.
  2. M. Yasin, B. Mazumdhar, O. Sinanoglu, and J. Rajendran, Removal Attacks on Logic Locking and Camouflaging Techniques, accepted in IEEE Transactions on Emerging Topics in Computing.
  3. M. Yasin, O. Sinanoglu, and J. Rajendran, Testing the Trustworthiness of IC Testing: An Oracle-less Attack on IC Camouflaging, accepted in IEEE Transactions on Information Forensics and Security.
  4. S. Ali, M. Ibrahim, J. Rajendran, O. Sinanoglu, and K. Chakrabarty, Supply-Chain Security of Digital Microfluidic Biochips, IEEE Computer Magazine, Volume 49, Issue 8, Pages 36-43, 2016.
  5. S. E. Zeltmann, N. Gupta, N. Tsoutsos, M. Maniatakos, J. Rajendran, and R. Karri, Manufacturing and Security Challenges in 3D printing, Journal of Materials, Volume 68, Issue 7, Pages 1872-1881, 2016. (Most read paper in Springer Engineering in 2016)
  6. J. Rajendran, O. Sinanoglu, and R. Karri, Building trustworthy systems using untrusted components: A High-level synthesis approach, IEEE Transactions on Very Large Scale Integration Systems, Volume 24, Issue 9, Pages 2946-2959, 2016.
  7. M. Yasin, J. Rajendran, O. Sinanoglu, and R. Karri, On Improving the Security of Logic Locking, IEEE Transactions on Computer-Aided Design, Volume 35, Issue 9, Pages 1411-1424, 2015.
  8. J. Rajendran, A. Ali, O. Sinanoglu, and R. Karri, Belling the CAD: Towards Security-Centric Electronic System Design, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Volume 34, Issue 11, Pages 1756-1769, 2015.
  9. J. Rajendran, Ramesh Karri, James B.Wendt, Miodrag Potkonjak, Nathan McDonald, Garrett S. Rose, and Bryant Wysocki, Exploring Nanoelectronic Devices for Security Applications, Proceedings of the IEEE, Volume 103, Issue 5, Pages 829-849, 2015.
  10. J. Rajendran, R. Karri, and G.S. Rose, Improving Tolerance to Variations in Memristor-based Applications Using Parallel Memristors, IEEE Transactions on Computers, Volume 64, Issue 3, Pages 733-746, 2015.
  11. J. Rajendran, H. Zhang, C. Zhang, G.S. Rose, Y. Pino, O. Sinanoglu and R. Karri, Fault Analysis-based Logic Encryption, IEEE Transactions on Computers, Volume 64, Issue 2, Pages 410-424, 2015. (Popular paper in IEEE Transactions on Computers, Nov. 2016)
  12. Chen Liu, J. Rajendran, Chengmo Yang and Ramesh Karri, Shielding Heterogeneous MPSoCs from Untrustworthy 3PIPs through Security-Driven Task Scheduling, IEEE Transactions on Emerging Topics in Computing, Volume 2, Issue 4, Pages 461-472, 2014.
  13. J. Rajendran, O. Sinanoglu, and R. Karri, Regaining Trust in VLSI Design: Design-for-Trust Techniques, Proceedings of the IEEE, Volume 102, Issue 8, Pages 1266-1282, 2014.
  14. J. Rajendran, A. K. Kanuparthi, M. Zahran, S. Addepalli, G. Ormazabal, and R. Karri, Securing processors against insider attacks: a circuit-microarchitecture co-design approach, IEEE Design and Test Magazine (Special Issue on Trusted SoC with Untrusted Components), Volume 30, Issue 2, Pages 35-44, 2013.
  15. S. Kannan, J. Rajendran, O. Sinanoglu, and R. Karri, Sneak Path Testing of Crossbar-based Non-volatile Random Access Memories, IEEE Transactions on Nanotechnology, Volume 12, Issue 3, Pages 413-426, 2013.
  16. J. Rajendran, H. Manem, R. Karri and G.S. Rose, An Energy-Efficient Memristive Threshold Logic Circuit, IEEE Transactions on Computers, Volume 61, Issue 4, Pages 474-487, 2012.
  17. G.S. Rose, H. Manem, J. Rajendran, R. Karri and R. Pino, Leveraging Memristive Systems in the Construction of Digital Logic Circuits, Proceedings of the IEEE, Volume 100, Issue 6, Pages 2033-2049, 2012.
  18. H. Manem, J. Rajendran and G.S. Rose, Design Considerations for Multi-Level CMOS/Nano Memristive Memory, ACM Journal of Emerging Technologies in Computing, Volume 8, Issue 1, Pages 6:1-6:22, 2012.
  19. H. Manem, J. Rajendran, and G.S. Rose, Stochastic Gradient Descent Inspired Training Technique for a CMOS/Nano Memristive Trainable Threshold Gate Array, IEEE Transactions on Circuits and Systems-I, Volume 59, Issue 5, Pages 1051-1060, 2012.
  20. M. Tehranipoor, H. Salmani, X. Zhang, X. Wang, R. Karri, J. Rajendran and K. Rosenfeld, Trustworthy Hardware: Trojan Detection and Design-for-Trust Challenges, Computer Magazine, Volume 44, Issue 7, Pages 66-74, 2011.
  21. R. Karri, J. Rajendran, K. Rosenfeld and M. Tehranipoor, Trustworthy Hardware: Identifying and Classifying Hardware Trojans, Computer Magazine, Volume 43, Issue 10, Pages 39-46, 2010.

Conferences

  1. Wenbin Xu, Lang Feng, Jeyavijayan Rajendran, and Jiang Hu,”Layout Recognition Attacks on Split Manufacturing” accepted at the Asia and South Pacific Design Automation Conference, 2019.
  2. Nithyashankari Jayasan, Adriana Sanbria, Jiang Hu, Edgar Sanchez-Sinencio, Jeyavijayan J. V. Rajendran, “Towards provably-secure analog and mixed-signal locking against overproduction” accepted at the IEEE/ACM International Conference on Computer-Aided Design, 2018.
  3. Monir Zaman, Abhrajit Sengupta, Danqing Liu, Ozgur Sinanoglu, Yiorgos Makris, Jeyavijayan J. V. Rajendran, “Towards provably-secure performance locking,” in the Proceedings of  Design Automation and Test in Europe, 2018.
  4. M. Yasin, A. Sengupta, M. Ashraf, M. Nabeel, J. Rajendran, and O. Sinanoglu, “Provably-secure Logic Locking: From Theory To Practice,” accepted at ACM Conference on Computer and Communications Security, 2017.
  5. M. Algappan, J. Rajendran, M. Doroslovacki, and G. Venkataramani, “DFS Covert Channels on Multi-Core Platforms,” accepted at IEEE Symposium on VLSI-SoC, 2017.
  6. Y. Wang, T. Cao, J. Hu, and J. Rajendran, “Front-End of Line Attacks in Split Manufacturing,” accepted in the Proceedings of IEEE/ACM International Conference on Computer-Aided Design, 2017.
  7. L. Feng, Y. Wang, W-K. Mak, J. Rajendran, J. Hu, “Making Split Fabrication Synergistically Secure and Manufacturable,” accepted in the Proceedings of IEEE/ACM International Conference on Computer-Aided Design, 2017.
  8. M. Yasin, A. Sengupta, B. Schäfer, Y. Makris, O. Sinanoglu, J. Rajendran, “What to Lock?: Functional and Parametric Locking,” in the Proceedings of the ACM Great Lakes Symposium on VLSI, Pages 351-356, 2017.
  9. Y. Wang, J. Hu, and J. Rajendran, “Routing perturbation for enhanced security in split manufacturing,” in the Proceedings of IEEE Asia and South Pacific Design Automation Conference, Pages 605-610, 2017.
  10. M. Yasin, B. Mazumdhar, O. Sinanoglu, and J. Rajendran, “Security analysis of Anti-SAT,” in the Proceedings of IEEE Asia and South Pacific Design Automation Conference, Pages 342-247, 2017.
  11. Md. B. Majumder, M. Uddin, J. Rajendran, and G. Rose, “Sneak Path Enabled Authentication for Memristive Crossbar Memories,” in the Proceedings of IEEE Asian Hardware Oriented Security and Trust Symposium, 2016.
  12. C. Yang, B. Liu, W. Wen, M. Barnell, Q. Wu, H. Li, Y. Chen, and J. Rajendran, “Security of Neuromorphic Computing: Thwarting learning attacks using memristor’s obsolescence effect,” in the Proceedings of IEEE International Conference on Computer-Aided Design, Pages 97:1-97:6, 2016.
  13. M. Yasin, B. Mazumdhar, O. Sinanoglu, and J. Rajendran, “CamoPerturb: Secure IC Camouflaging for Minterm Protection,” in the Proceedings of IEEE International Conference on Computer-Aided Design, Pages 29:1-29:8, 2016.
  14. M. Yasin, B. Mazumdhar, O. Sinanoglu, and J. Rajendran, “SARLock: Resisting SAT attacks on Logic encryption,” in the Proceedings of IEEE Symposium on Hardware Oriented Security and Trust, Pages 236-241, 2016.
  15. M. Bidmeshki, G. Reddy, L. Zhou, J. Rajendran, and Y. Makris, “Hardware-based attacks to compromise the cryptographic security of an election system”, in the Proceedings of IEEE International Conference on Computer Design, Pages 153-156, 2016.
  16. A. Kanuparthi, J. Rajendran, and R. Karri, “Controlling your control flow graph,” in the Proceedings of IEEE Symposium on Hardware Oriented Security and Trust, Pages 43-48, 2016.
  17. Y. Wang, P. Chen, J. Hu, and J. Rajendran, “The Cat and Mouse in Split Manufacturing,” in the Proceedings of IEEE/ACM Design Automation Conference, Pages 165:1-165:6, 2016.
  18. J. Tang, J. Rajendran, and R. Karri, “Securing Pressure Measurements Using SensorPUFs,” in the Proceedings of IEEE International Symposium on Circuits and Systems, Pagees 1330-1333, 2016.
  19. M. Yasin, S. Saeed, J. Rajendran, and O. Sinanoglu, “Activation of Logic Encrypted Chips: Pre-Test or Post-Test?,” in the Proceedings of IEEE/ACM Design Automation and Test in Europe, Pages 139-144, 2016.
  20. J. Rajendran, A. M. Dhandayuthapany, V. Vedula, and R. Karri, Security Verification of 3rd Party Intellectual Property Cores for Information Leakage, in the Proceedings of IEEE International Conference on VLSI Design, Pages 547-552, 2016.
  21. J. Rajendran, V. Vedula, and R. Karri, Detecting Malicious Modifications of Data in Third-Party Intellectual Property Cores, in the Proceedings of IEEE/ACM Design Automation Conference, Pages 112:1–112:6, 2015.
  22. D. Shahrjerdi, J. Rajendran, S. Garg, R. Karri, and F. Koushanfar, Shielding and Securing Integrated Circuits using Sensors, in the Proceedings of IEEE/ACM International Conference on Computer-Aided Design, Pages 170-174, 2014.
  23. D. Hoe, J. Rajendran, and R. Karri, Towards Secure Analog Designs: A Secure Sense Amplifier Using Memristors, in the Proceedings of IEEE International Symposium on VLSI, Pages 516-521, 2014.
  24. A.Waksman, J. Rajendran and S. Sethumadhavan A Red Team/Blue Team Assessment of Functional Analysis Methods for Malicious Circuit Identification, accepted in IEEE/ACM Design Automation Conference, Pages 1-4, 2014.
  25. J. Rajendran, M. Sam, O. Sinanoglu, and R. Karri, Security Analysis of Integrated Circuit Camouflaging, in the Proceedings of the ACM Conference on Computer and Communications Security, Pages 709-720, 2013. (Best Student Paper Award)
  26. M. Rostami, F. Koushanfar, J. Rajendran and R. Karri, Hardware Security: Threat Models and Metrics, in the Proceedings of IEEE Conference on Computer-Aided Design, Pages 819-823, 2013.
  27. C. Liu, J. Rajendran, C. Yang and R. Karri, Shielding Heterogeneous MPSoCs from Untrustworthy 3PIPs through Security-Driven Task Scheduling, in the Proceedings of IEEE Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, Pages 101-106, 2013. (Best Student Paper Award)
  28. J. Rajendran, O. Sinanoglu, and R. Karri, VLSI Testing based Security Metric for IC Camouflaging, in the Proceedings of the IEEE International Test Conference, Pages 1-4, 2013.
  29. O. Sinanoglu, N. Karimi, J. Rajendran, R. Karri, Y. Jin, K. Huang, and Y. Makris, Reconciling the IC Test and Security Dichotomy, in the Proceedings of IEEE European Test Symposium, Pages 1-6, 2013.
  30. J. Rajendran, H. Zhang, O. Sinanoglu, and R. Karri, High-Level Synthesis for Security and Trust, in the Proceedings of the IEEE International On-Line Testing Symposium, Pages 232-233, 2013.
  31. X. Zhang, K. Xiao, M. Tehranipoor, J. Rajendran, and R. Karri, A study on the effectiveness of Trojan detection techniques using a red team blue team approach, in the Proceedings of IEEE VLSI Test Symposium, Pages 1-3, 2013.
  32. J. Rajendran, O. Sinanoglu, and R. Karri, Is Split Manufacturing secure?, in the Proceedings of the IEEE/ACM Design Automation and Test Conference, Pages 1259-1264, 2013.
  33. G. Rose, J. Rajendran, N. McDonald, R. Karri, M. Potkonjak, and B. Wysocki, Hardware Security Strategies Exploiting Nanoelectronic Circuits, in the Proceedings of IEEE/ACM Asia and South Pacific Design Automation Conference, Pages 368-372, 2013.
  34. S. Kannan, J. Rajendran, O. Sinanoglu, and R. Karri, Sneak Path Testing of Memristor-based Memories, in the Proceedings of IEEE International Conference on VLSI Design, Pages 386-391, 2013.
  35. J. Rajendran, G. S. Rose, R. Karri, and M. Potkonjak, Nano-PPUF: A Memristor-based security primitive, in the Proceedings of IEEE International Symposium on VLSI, Pages 84-87, 2012.
  36. J. Rajendran, Y. Pino, O. Sinanoglu, and R. Karri, Security Analysis of Logic Obfuscation, in the Proceedings of IEEE/ACM Design Automation and Conference, Pages 83-89, 2012.
  37. J. Rajendran, Y. Pino, O. Sinanoglu, and R. Karri, Logic encryption: A fault analysis perspective, in the Proceedings of IEEE/ACM Design Automation and Test in Europe, Pages 953-958, 2012.
  38. J. Rajendran, Y. Pino, O. Sinanoglu, and R. Karri, Applying IC Testing Concepts to Secure ICs, in the Proceedings of GOMACTECH, 2012.
  39. S. Kannan, J. Rajendran, O. Sinanoglu, and R. Karri, Engineering Crossbar based Emerging Memory Technologies, in the Proceedings of IEEE International Conference on Computer Design, Pages 478-479, 2012.
  40. J. Rajendran, V.Jyothi, O.Sinanoglu, and R. Karri, Design and analysis of ring oscillator based Design for-Trust technique, in the Proceedings of IEEE VLSI Test Symposium, Pages 105-110, 2011.
  41. J. Rajendran, V. Jyothi, and R. Karri, Blue team red team approach to hardware trust assessment: The embedded systems challenge experience, in the Proceedings of IEEE International Symposium on Computer Design, Pages 285-288, 2011.
  42. J. Rajendran, R. Karri, and G.S. Rose, Parallel Memristors: Improving Variation Tolerance in Memristive Digital Circuits, in the Proceedings of IEEE International Symposium on Circuits and Systems, Pages 2241-2244, 2011.
  43. J. Rajendran, H. Manem, R. Karri and G.S. Rose, An Approach to Tolerate Process Related Variations in Memristor-based Applications, in the Proceedings of IEEE Symposium on VLSI Design, Pages 18-23, 2011. (Best Student Paper Award)
  44. J. Rajendran, H. Manem, R. Karri and G.S. Rose, Memristor based Programmable Threshold Logic Array, in the Proceedings of IEEE Symposium on Nanoscale Architectures, Pages 5-10, 2010.
  45. J. Rajendran, H. Borad, S. Mantravadi and R. Karri, SLICED: Slide-based Concurrent Error Detection Technique for Symmetric Block Ciphers, in the Proceedings of IEEE Symposium on Hardware Oriented Security and Trust, Pages 70-75, 2010.
  46. J. Rajendran, J. Jimenez, E. Gavas, V. Padman and R. Karri, Towards a comprehensive and systematic classification of hardware Trojans, in the Proceedings of IEEE Symposium on Circuits and Systems, Pages 1871-1874, 2010.
  47. J. Rajendran, H. Manem and G.S. Rose, NDR based threshold logic fabric with memristive synapses, in the Proceedings of IEEE-NANO, Pages 725-728, 2009.