Department of Electrical and Computer Engineering

The Computer Engineering and Systems Group

Controlling On-chip (Capacitive) and Off-chip (Inductive) Crosstalk

 


In the last decade, capacitive (as well as inductive) cross-talk in VLSI ICs has become significantly aggravated for on-chip (off-chip) bus signals. My group published the first papers to address these issues by using coding techniques. Our work on the use of coding techniques to mitigate the impact of inductive cross-talk allows a VLSI IC manufacturer to utilize less expensive wire-bond packages for high-speed applications, which was earlier infeasible. I am told that a leading IC manufacturer is using this technique in their ICs.

 

We have developed capacitive cross-talk canceling approaches (both memory-based and memoryless), which can be used to trade off the degree of cross-talk cancellation desired against the tolerable area overhead. Cross-talk canceling CODECs traditionally do not synthesize well, and exhibit an exponential increase in gate count with increasing bus size. We have developed Fibonacci Numeral System (FNS) based techniques to reduce this to a quadratic increase, for both Forbidden Pattern Free (FPF) and Forbidden Transition Free (FTF) cross-talk avoidance codes. In addition, we have developed a ternary bus, which has improved power, delay and energy compared to other bus encoding techniques.

By modeling the inductive parasitics in the off-chip signal path, we have developed models for bus performance as well inductive cross-talk canceling codes (which allow the user to trade off the area overhead against the degree of cross-talk cancellation desired). Another inductive cross-talk cancellation approaches utilizes “stuttering” to improve inductive cross-talk. In addition, we have developed broadband impedance matching approaches which allow the designer to match the impedance of the IO signal path with the characteristic impedance of the board wires. This effort received a best paper award at ICCD 2005.

Publications, patents and artefacts:

  • “Analysis and Avoidance of Cross-talk in On-Chip Buses”, Duan, Tirumala, Khatri. Published at IEEE Symposium on High-Performance Interconnects (HOT Interconnects 2001), August 22-24, 2001, pp 133-138, Stanford, CA, pp. 133-138. This paper described how on-chip cross-talk can be canceled by encoding techniques, for 4C and 3C crosstalk sequences, providing analytical bounds on the number of extra wires required to achieve this degree of crosstalk avoidance. This was the first paper in this area.Presentation slides.
  • “Exploiting Crosstalk to Speed up On-chip Buses”, Duan, Khatri. Design Automation and Test in Europe (DATE) conference, February 2004, pp. 778-783. In this paper, we developed newer coding approaches which used cross-talk to speed up a bus. The paper provides techniques to eliminate 2C crosstalk as well. Presentation slides.
  • “Memory-based Cross-talk Canceling CODECs for On-chip Buses”, Duan, Gulati, Khatri. IEEE International Symposium on Circuits and Systems (ISCAS), May 21-24 2006, Kos, Greece, pp. 1119-1122. This paper reports an approach to automatically generate a codebook for on-chip cross-talk immune memory-based codes with a user-specified level of cross-talk tolerance. This paper shows that a bus can be sped up by a factor of up to 6X using memory-based CODECs, with a reduced overhead compared to memoryless CODECs. Presentation slides.
  • “Forbidden Transition Free Crosstalk Avoidance CODEC Design”, Duan, Khatri. ACM/EDAC/IEEE Design Automation Conference (DAC) 2008, June 8-13 2008, Anaheim, CA, pp. 986-991. Cross-talk avoidance CODECs typically grow exponentially in size as the number of bits increases. In this paper, we utilize a Fibonacci Numeral System (FNS) based CODEC, which grows quadratically in size with a growth in the bus size. Presentation slides.
  • “Efficient On-Chip Crosstalk Avoidance CODEC Design”, Duan, Cordero, Khatri. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, April 2009, vol 17, number 4, pp 551-560. This paper reports an efficient design for forbidden pattern free ( FPF) cross-talk avoidance CODECs, with significantly lower area utilization than competing approaches. Our CODECs achieve the theoretical minimum area overhead performance.
  • “Encoding-based Minimization of Inductive Cross-talk for Off-chip Data Transmission”, LaMeres, Khatri. Design Automation and Test in Europe (DATE) conference, March 2005, pp. 1318-1323. In this paper, we described how encoding can be used to cancel inductive effects, and speed up an off-chip bus. Our approach improves bus bandwidth by 85%, with an asymptotic bus overhead between 30% and 50% depending on the degree of desired crosstalk avoidance. This was the first paper in this area. Presentation slides.
  • “Broadband Impedance Matching for Inductive Interconnect in VLSI Packages”, LaMeres, Khatri. International Conference on Computer Design (ICCD) 2005, Oct 2-5, San Jose, CA, pp. 683-688. Best Paper Award, ICCD 2005 In this paper, we describe techniques to match the impedance of off-chip signals with the characteristic impedance of the board traces. The approach reduces transmission line reflections (from 20% to 5% for uncompensated buses for board traces up to 5mm in length). Presentation slides.
  • “Controlling Inductive Cross-talk and Power in Off-chip Buses using CODECs”, LaMeres, Gulati, Khatri. Asia Pacific Design Automation Conference (ASPDAC) 2006, January 24-27, Yokohama, Japan, pp. 850-855. This paper presents a method to reduce inductive cross-talk in off-chip buses, by encoding the data to reduce transitions that induce inductive cross-talk induced voltage glitches. Using our approach improves bus bandwidth by over 100% over an unencoded bus, as demonstrated by SPICE simulations as well as an FPGA prototype. Presentation slides.
  • “Impedance Matching Techniques for VLSI Packaging”, LaMeres, Garg, Gulati, Khatri. DesignCon 2006, February 6-9, 2006, Santa Clara, CA. In this paper, we explore techniques package-level techniques to match the impedance of off-chip traces with that of the driving circuitry (on chip as well as in the package). The approach reduces transmission line reflections from 20% to 5%, for flip-chip as well as wire-bond packages. Presentation slides.
  • “Bus Stuttering : An Encoding Technique to Reduce Inductive Noise in Off-Chip Data Transmission”, LaMeres, Khatri. Design Automation and Test in Europe (DATE) conference, March 6-10 2006, Munich, Germany, pp. 522-527. This paper presents a technique to introduce stutter states in an off-chip data bus, in order to reduce inductance induced cross-talk noise. The bus bandwidth increases by about 225% when using this approach. Presentation slides.
  • “Energy Efficient and High Speed On-Chip Ternary Bus”, Duan, Khatri. Design Automation, and Test in Europe (DATE) Conference 2008, 10-14 March, Munich, Germany, pp. 515-518. This paper reports a high speed bus with 3 voltage levels. Data bits transmitted on the bus are still binary valued, but utilize one of the 3 voltages opportunistically during transmission to yield a reduced energy, delay as well as power over previous solutions. Presentation slides.
  • “Performance Model for Inter-chip Communication Considering Inductive Cross-talk and Cost”, LaMeres, Khatri. IEEE International Symposium on Circuits and Systems, Kobe, Japan, May 23 – 26 2005, pp. 4130-4133. This paper shows that bus throughput reaches an asymptotic limit as channels are added, and shows that the optimal number of channels is low (4-8). Presentation slides.
  • “Performance Model for Inter-Chip Busses Considering Bandwidth and Cost” LaMeres, Khatri. DesignCon East, Sept 19-21, Worcester, MA.Best Paper Award, DesignCon 2005. This paper evaluates various off-chip bus configurations, and compares them in terms of the (total as well as per-wire) throughput they offer for various packaging methods.
  • “On and Off-chip Cross-talk Avoidance in VLSI Designs”, Duan, LaMeres, Khatri. Monograph published by Springer Publishers. 1st edition, 2010. 240p. ISBN 978-1-4419-0946-6.
  • “Cross-talk Noise Immune VLSI Design using Regular Layout Fabrics”, Khatri, Brayton, Sangiovanni-Vincentelli. Research Monograph published by Kluwer Academic Publishers. ISBN # 0-7923-7407-X.