Lowering CMP Interconnect Power while Improving Performance:

Power is of paramount importance in modern computer system design.  In particular, the cache interconnect in future CMP designs is projected to consume up to half of the system power for  cache fills and spills. Despite the power consumed by spills and fills, a significant percentage of each cache line is unused prior to eviction from the cache.  If unused cache block words can be identified, this information can be used to improve CMP interconnect power and energy consumption.  We will explore new methods of CMP interconnect packet composition, leveraging unused data to reduce power.  These methods must be well suited to interconnection networks with high-bandwidth wires, and not require expensive multi-ported memory systems.

Performance in Multi-synchronous Networks-on-Chip:

Networks-on-Chip (NoC) have emerged as a replacement for traditional shared-bus designs for on-chip communications.  As with all current VLSI designs, however, reducing power consumption in NoCs is a critical challenge.  One approach to reduce power is to dynamically scale the voltage and frequency of each network node or groups of nodes (DVFS). Another approach to reduce power consumption is to replace the balanced clock tree with a globally-asynchronous, locally-synchronous (GALS) clocking scheme.  NoCs implemented with either of these schemes, however, tend to have high latencies as packets must be synchronized at intermediate nodes between source and destination.  We are investigating novel router microarchitectures which offer superior performance versus typical synchronizing router designs.  Our approach features Asynchronous Bypass Channels (ABCs) at intermediate nodes thus avoiding synchronization delay.  We are also examining new network topology and routing algorithms that leverage the advantages of the bypass channel offered by our router design.