Ocin_Tsim – On Chip Interconnect Network Timing Simulator (Ocin_tsim for short) is a flexible, extensible and cycle accurate timing simulator for packet switched interconnect networks.

PARSEC benchmarks in M5 – An in depth tech report on running PARSEC v2.1 in the M5 Simulator. Includes PARSEC benchmarks on  a disk images ready to run on M5, as well as directions on how to compile from scratch.