ECEN 6003 — Digital Circuit Design
Instructor Sunil P Khatri Office: ECOT432 Phone: 5-1962 E-mail: email@example.com Class time : N.A. (tape library course) Office Hours: M 1:00pm - 2:00pm F 1:00pm - 2:00pm or by appointment
- Course Objective
- Course Outline
- Software Tools
- Homework, Exams, Handouts, and Grading
- Lecture Notes, Homework, and other Postings
- Project related material
This course covers several aspects of digital circuit design. Starting with device equations, we will delve into several areas of digital circuit design, including recent changes in circuit design styles and future trends in digital circuit design.
The goal of the class is to take you through a tour of the issues a typical circuit designer in industry deals with, and the design techniques they utilize. The focus is on custom digital VLSI design. At the end of this class, you would have at your disposal an understanding of the analysis techniques and tools that are required for a VLSI circuit designer to effectively function in today’s industry.
Graduate standing, or upper division undergraduate standing, with some previous course or practical experience in VLSI devices and layout. If you dont meet the requisites and are still very interested in the class, please see me.
Overview of device fundamentals Gate and wire delays and their shift in importance. Different circuit design styles NMOS static CMOS dynamic CMOS Pass Transistor design PLAs SOI implications GaAs implications Simulating critical paths on a large chip long data/address paths memories. Memory design fundamentals types of memory cells design considerations for memory 3-Dimensional capacitive parasitics. reasons for their importance using 3-d extractors Transmission lines on-chip clock nets board nets Packaging issues inductive effects different packaging technologies. economic considerations of different package styles Off-chip I/O drivers design considerations On-chip clock distribution and generation schemes. Phas locked loops H-tree clock distribution Processing variations and their effects. Product Engineering Schmoo plots Differences in design approaches between arrayed and random logic. Power / ground distribution and noise.
The class project and some homeworks will involve hands-on use of SPICE (a circuit simulator), SPACE-3D (a 3-D parasitic extractor). SPICE can be run on Linux systems, and SPACE-3D on Linux/Solaris/HP systems.
Students will be given accounts on machines in CU where these tools are installed. Additionally, if students want to install these tools on their own machines at home, instructions will be provided on this web-site.
The class will be taught from notes which will be distributed on this website. These notes draw from several sources, and can be considered comprehensive. If you prefer to buy a textbook for your reference, you may consider these text books, in order of utility
- Principles of CMOS VLSI Design – a systems perspective – Weste and Eshraghian
- Digital Integrated Circuits – A Design Perspective – Rabaey
- The design and analysis of VLSI circuits – Glasser and Dobberpuhl.
20% 4-6 Homework assignments 40% 2 Mid-term assignments 40% Research-oriented class project in lieu of final exam. The class project is one of the most important parts of this class. It will enable you to dive deeper into a particular topic from the class.
Homework will be assigned at the start of the summer term and will be due before the end of the term. You are encouraged to turn in homework in a timely fashion so that you can stay abreast with the class material. You are welcome to work together on homework, but you should not turn in identical solutions, or one solution for multiple students.
Set 10 in ppt format.
Homework assignments and solutions:
Sunil P Khatri / University of Colorado at Boulder / firstname.lastname@example.org