Radiation and Process Variation Tolerance
Modern VLSI fabrication processes have minimum feature sizes in the deep sub-micron (DSM) range. These processes are plagued by an increased susceptibility to radiation induced failures as well as performance unpredictability due to processing variations. We have worked on techniques to analytically predict the effect of these two factors, as well as to devise design approaches to mitigate their impact on the electrical characteristics of the design. The focus is both on combinational as well as sequential designs. Part of this work is funded by a $7.5M multi-investigator NSF proposal lead by the Nuclear Engineering department at TAMU. Our goal in this project is to fabricate a solid-state radiation detector platform using the radiation hardening ideas we developed.
We have developed architectural as well as circuit level approaches for radiation tolerant VLSI design. In addition, we have developed fast analytical techniques to model the effect of radiation events on SRAMs as well as logic gates. Our techniques accurately and efficiently predict the shape of the radiation induced voltage pulse. More recently, we have been focus sing on radiation effects in clock circuits (PLLs as well as local clock regenerators), as well as radiation effects in voltage scaled circuits.
We have developed an accurate approach to perform sensitizable statistical timing analysis (StatSense), which eliminates the pessimism of SSTA arising from its use of static timing analysis. In addition, we have developed processing variation tolerant pulsed flip-flop designs, voltage level shifters as well as structured ASIC design approaches.
Publications, patents and artefacts:
- “Circuit-level Design Approaches for Radiation-hard Digital Electronics”, Garg, Jayakumar, Khatri, Choi. Accepted for publication at the IEEE Transactions on Very Large Scale Integration Systems. This paper presents a circuit level approach for radiation hardening, using shadow gates and a pair of diodes to achieve radiation tolerance. The approach in this paper achieves radiation hardening with a 3% delay overhead and about 28% area overhead compared to an unprotected circuit.
- “A Design Approach for Radiation-hard Digital Electronics”, Garg, Jayakumar, Khatri. ACM/IEEE Design Automation Conference (DAC), July 24-28 2006, pp. 773-778. In this paper, we present a diode pair based approach to implement radiation hardened digital circuits, with a 4% delay overhead and about 30% area overhead compared to an unprotected circuit. Presentation slides.
- “A Novel, Highly SEU Tolerant Digital Circuit Design Approach”, Garg, Khatri. IEEE International Conference on Computer Design (ICCD) 2008, Lake Tahoe, CA, October 12-15 2008, pp. 14-20. This paper presents a radiation hardened approach to design logic circuits, with extreme high levels (up to 650 fC for 1.5GHz operation) of radiation tolerance. Presentation slides.
- “A Delay-Efficient Radiation-Hard Digital Design Approach Using CWSP Elements”, Nagpal, Garg, Khatri. Design Automation, and Test in Europe (DATE) Conference 2008, 10-14 March, Munich, Germany, pp. 354-359. In this paper, we present an architecture-level approach to implement radiation hardened circuits with minimal delay overhead. Our approach provides a high degree of radiation tolerance, with a 1% delay overhead.
- “SEU Hardened Clock Regeneration Circuits”, Dash, Garg, Khatri, Choi. International Symposium on Quality Electronic Design (ISQED) San Jose, CA. Mar 16-18 2009. Radiation hardening for clock circuits has received little attention to date. In this paper, we design a highly radiation tolerant clock regenerator circuit. Our method removes radiation induced clock races, and reduces radiation induced jitter to 30ps for radiation strikes up to 150fC. Presentation slides.
- “A Radiation Tolerant Phase Locked Loop Design for Digital Electronics”, Kumar, Karkala, Garg, Jindal, Khatri. IEEE International Conference on Computer Design (ICCD) 2009, Lake Tahoe, CA. October 4-7, 2009. In this paper, we present a radiation hardened analog PLL, in which every node is radiation hardened by using a novel split output design approach. The worst case radiation induced jitter is 18%. The PLL requires 16 cycles to lock after the worst case radiation event, a significant improvement over previous radiation hardened PLLs.
- “Modeling Dynamic Stability of SRAMs in the Presence of Single Event Upsets (SEUs)”, Garg, Li, Khatri. IEEE International Symposium on Circuits and Systems, 18-21 May 2008, Seattle, WA, pp. 1788-1791. This paper presents an accurate analytical model for SRAM stability in the presence of radiation strikes. The approach achieves accuracy within 2.5% of SPICE, with a 1200X speedup over SPICE.
- “A Fast, Analytical Estimator for the SEU-induced Pulse Width in Combinational Designs”, Garg, Nagpal, Khatri. ACM/ EDAC/IEEE Design Automation Conference (DAC) 2008, June 8-13 2008, Anaheim, CA, pp. 918-923. This paper presents a highly accurate analytical model to estimate the pulse width of a radiation induced glitch in logic gates. Our method achieves an accuracy of within 4% of SPICE, with a speedup of over 1000X over SPICE. Presentation slides.
- “Efficient Analytical Determination of the SEU-induced Pulse Shape”, Garg, Khatri. IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC) 2009, Yokohama, Japan, Jan 19-22 2009, pp. 461-467. In this paper, we present a fast, accurate analytical approach to estimate the shape of the voltage glitch that is generated at the output of a logic gate, when a radiation particle strikes the gate. Our method achieves a root mean square percentage error in computing the SEU induced glitch waveform of no more than 4.5% of SPICE, with a speedup of over 275X over SPICE. Nominated for best paper award Presentation slides.
- “3D Simulation and Analysis of the Radiation Tolerance of Voltage Scaled Digital Circuits”, Garg, Khatri. IEEE International Conference on Computer Design (ICCD) 2009, Lake Tahoe, CA. October 4-7, 2009. In this paper, we conduct 3D device simulations to find the collected charge due to a radiation strike as a function of the chip operating voltage as well as the particle energy. The paper shows that for radiation tolerance, the supply voltage should be maintained about 600mV, and also provides an analytical model for the amount of collected charge from a radiation strike. Presentation slides.
- “On the Improvement of Statistical Static Timing Analysis”, Garg, Jayakumar, Khatri. IEEE International Conference on Computer Design (ICCD), Oct 1-4, 2006, San Jose, CA, pp. 37-42. This paper presents sensitizable SSTA, in which the pessimism of traditional SSTA (due to the inclusion of false paths and also the lack of knowledge of the vector transition being simulated) is erased. The pessimism of traditional SSTA can be as high as 20% and can be erased with this approach. Presentation slides.
- “A Single-Supply True Voltage Level Shifter”, Garg, Mallarapu, Khatri. Design Automation, and Test in Europe (DATE) Conference 2008, 10-14 March, Munich, Germany, pp. 979-984. This paper presents a variation tolerant level shifter for use when signals in an IC traverse different voltage domains. The novel feature of our converter is that it works for high-to-low as well as low-to-high voltage domain conversions, in a process, voltage and temperature tolerant manner. This paper was implemented in silicon, to design level shifters at LSI Logic Presentation slides.
- “A Variation Tolerant Circuit Design Approach using Parallel Gates”, Garg, Khatri. Austin Conference on Integrated Systems and Circuits (ACISC) 2009, Austin, TX. October 26-27, 2009. This paper shows that implementing gates with parallel transistors yields significant improvements in variability with minimal area cost.
- “A Robust Pulsed Flip-Flop and its use in Enhanced Scan Design”, Kumar, Bollapalli, Garg, Soni, Khatri. IEEE International Conference on Computer Design (ICCD) 2009, Lake Tahoe, CA. October 4-7, 2009. This paper reports a variation tolerant pulsed flip flop which is capable of being used as an enhanced scan flip-flop. The flip flop is faster, smaller and consumes less power than a traditional enhanced scan flip-flop.
- “An Efficient Pulse Flip-Flop Based Launch-on-Shift Scan Cell”, Kumar, Bollapalli, Khatri. IEEE International Symposium on Circuits and Systems (ISCAS) 2010, Paris, France. May 30 – Jun 2, 2010. This paper reports on a launch-on-shift scan flip-flop, implemented using a pulsed latch. Our design is faster, smaller and less power hungry (by upwards of 20%) than the existing method of designing such a scan cell.
- “A Robust, Fast Pulsed Flip-Flop Design”, Venkatraman, Garg, Khatri. IEEE Great Lakes Symposium on VLSI, May 4-6, 2008, Orlando, FL, pp. 119-122. This paper presents a variation tolerant pulsed flip-flop design, with lower power and area than existing flip-flop designs. Our flip-flop provides better speed and improved variation tolerance compared to existing pulsed flip-flops as well as traditional D flip-flops.Presentation slides.
- “A Lithography-friendly Structured ASIC Design Approach”, Gopalani, Garg, Khatri, Cheng. IEEE Great Lakes Symposium on VLSI, May 4-6, 2008, Orlando, FL, pp. 315-320. In this paper, we present a structured ASIC design approach using NAND2 gates, with superior lithographic characteristics and very low delay (40%), power (7%) and area (12%) overheads compared to ASIC designs. Presentation slides.
- “Analysis and Design of Resilient VLSI Circuits: Mitigating Soft Errors and Process Variations”, Garg, Khatri. Monograph published by Springer Publishers. 1st edition, 2010. 212p. ISBN 978-1-4419-0930-5