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CESG Seminar: Entangling Prefetchers

October 22 @ 10:20 am - 11:10 am


Dr. Alberto Ros 
Full Professor in the Computer Engineering Department at the University of Murcia, Spain


Entangling Prefetchers


Talking Points:

      Entangling Prefetcher for Instructions won the 1st Instruction Prefetching Championship

      Entangling Prefetchers have a strong focus on timeliness



Prefetching instructions and data is a fundamental technique for designing high-performance computers. There are three key properties to consider when designing an efficient and effective prefetcher: timeliness, coverage, and accuracy. Timeliness is essential, as bringing instructions too early increases the risk of the instructions being evicted from the cache before their use and requesting them too late can lead to the instructions arriving after they are demanded. Coverage is important to reduce the number of instruction cache misses and accuracy to ensure that the prefetcher does not pollute the cache or interacts negatively with the other hardware mechanisms.

This talk introduces Entangling Prefetchers which have a focus on timeliness. We present an Entangling Prefetcher for Instructions, which works by finding which instruction should trigger the prefetch for a subsequent instruction, accounting for the latency of each cache miss. Our evaluation shows that with 40KB of storage, Entangling can increase performance up to 23% thereby outperforming state-of-the-art prefetchers.


Dr. Alberto Ros is full professor in the Computer Engineering Department at the University of Murcia, Spain. Funded by the Spanish government to conduct the PhD studies he received the PhD in Computer Science from the University of Murcia in 2009. He held postdoctoral positions at the Universitat Politècnica de València and Uppsla University. He received an European Research Council Consolidator Grant in 2018 to improve the performance of multicore architectures. Working on cache coherence, memory hierarchy designs, memory consistency, and processor microarchitecture, he has co-authored more than 80 peer-reviewed articles. He has been inducted into the ISCA Hall of Fame. He is an IEEE Senior member.










Zoom Meeting ID: 963 4348 1647


October 22
10:20 am - 11:10 am


Paul Gratz