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CESG Fishbowl Seminar: Metal Layer Planning for Silicon Interposers

June 3, 2013 @ 2:00 pm - 3:00 pm

Room 333 Wisenbaker Engr. Building (Fishbowl)

Dr. T.C. Wang, Professor
Department of Computer Science, National Tsing Hua University, Taiwan

A 2.5D IC provides a silicon interposer to integrate multiple dies into a package, which not only offers better performance and power-efficiency than 2D ICs but also has lower manufacturing complexity than true 3D ICs. For a 2.5D IC, the number of metal layers in its silicon interposer is one of the critical factors to affect its routability and manufacturing cost. Thus, how to achieve 100% routing completion rate in a silicon interposer using a minimum number of metal layers plays a key role for the success of an 2.5D IC. In this talk a global-routing-based metal layer planner to identify a minimal number of metal layers for a silicon interpose will be presented. The metal layer planner can also identify a good stacking order of the horizontal layers and vertical layers in a silicon interposer for less via count. Experimental results will be shown to demonstrate the robustness of the metal layer planner.

Bio: Ting-Chi Wang received the B.S. degree in computer science and information engineering from National Taiwan University, Taiwan, and the M.S. and Ph.D. degrees in computer sciences from the University of Texas at Austin, USA. He is currently a professor with the Department of Computer Science, National Tsing Hua University, Taiwan. His research interest is in VLSI physical design automation. Dr. Wang was the recipient of the Best Paper Award at 2006 ASP-DAC for his work on redundant via insertion. He supervised a team to win the first place at the 2008 ISPD Global Routing Contest. He has served on the technical program committees of major EDA conferences, including ASP-DAC, DATE, DAC, ICCAD, and ISPD. He is currently an Associate Editor of ACM Transactions on Design Automation of Electronic Systems.

Host: Dr. Hu


June 3, 2013
2:00 pm - 3:00 pm