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CESG Seminar: Power Gating with Block Migration in Chip-Multiprocessor Last-Level Caches

September 27, 2013 @ 3:00 pm - 4:00 pm

Room 1034 ETB

David Kadjo
Department of ECE, TAMU

In this seminar, I’ll present a technique to reduce the leakage energy of last level caches while mitigating any significant performance impact. In general, cache blocks are not ordered by their temporal locality within the sets; hence, simply power gating off a partition of the cache, as done in previous studies, may lead to considerable performance degradation. We propose a solution that migrates the high temporal locality blocks to facilitate power gating, where blocks likely to be used in the future are migrated from the partition being shutdown to the live partition at a negligible performance impact and hardware overhead. Our detailed simulations show energy savings of 66% at low performance degradation of 2.16%.

Bio: David Kadjo is currently is PhD candidate with the Electrical and Computer Engineering Department at Texas A&M University under the supervision of Dr. Paul Gratz. He received his Bachelor(s) in Electrical Engineering and Mathematics from the New Mexico Institute of Mining and Technology in 2005 and his Masters in Electrical Engineering from the University of Texas at El Paso in 2007. He worked as an application engineer with Texas Instruments from 2007 to 2009. His research focuses on power and performance on processors and mobile devices. He is done continuous work with Intel corporation since 2010 with the platform analysis and performance group and the strategic CAD lab working on platform power management on mobile devices.


September 27, 2013
3:00 pm - 4:00 pm