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CESG Seminar: SyNAPSE: Scalable Energy-Efficient Neurosynaptic Computing

March 28, 2014 @ 3:55 pm - 5:00 pm

Room 1034 ETB

Jun Sawada, IBM Austin Research Lab

SyNAPSE (Systems of Neurosynaptic Adaptive Plastic Scalable Electronics) is a project aiming to build a brain-like computing system in the scale of mammalian brains. The project team has been combining the principles of nanoscience, neuroscience and supercomputing to simulate and emulate the brain’s abilities for sensation, perception, action, interaction and cognition while rivaling its low power consumption and compact size.

Recently, we simulated a CoCoMac macaque network model with 10^14 synapses using a BlueGene/Q supercomputer. The simulation is more than 1000 times slower than real-time, and it consumes mega-watts of power. This study is a milestone in the simulation of a large-scale neural network, but this is not a path to scalable energy-efficient neurosynaptic computing. We need an approach to drastically reduce the power consumption from a typical von Neumann computing system.

Toward this goal, our team demonstrated a couple of ASIC neurosynaptic prototype chips. They represent synaptic connections by using SRAM as a crossbar between axon and dendrite circuits. One of them particularly is built using asynchronous circuits, and achieved an extremely low-power computation of 45pJ per spike. Asynchronous circuits do not require global clock trees and consumes only leak power when there is no activity on the chip. The team also published a model of neuron state computation that can be implemented with only 1272 ASIC gates, but still can emulate various logical and mathematical functions, as well as biologically-interesting neuron behaviors. We envision these will be the foundation of much larger energy-efficient neurosynaptic computing systems in the future.
(This research is funded by DARPA, Defense Advanced Research Projects Agency.)

Jun Sawada graduated from Kyoto University in Japan with BS and MS degrees in Mathematics. He received Ph.D in Computer Sciences from the University of Texas at Austin for the study of formal verification of hardware, VLSI micro-architecture, theorem proving and automated deduction. In 2000, he joined IBM Austin Research Laboratory, and he is an IBM research staff member since then. At IBM, he has been involved in various projects developing high-speed semiconductor chips including BlueGene/Q and POWER processors. Recently he is working on the SyNAPSE project, leading the design effort of neurosynaptic hardware.

Host: Dr. Hu



March 28, 2014
3:55 pm - 5:00 pm