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CESG Seminar: Techniques for Fast Physical Design Closure

October 10, 2014 @ 3:55 pm - 5:00 pm

Room 1034 ETB

Dr. Guo Yu
Oracle Corp.

Abstract: Continued trend in VLSI interconnect scaling is causing rapid rise in buffer count for modern digital integrated circuits. Besides increased power dissipation, the growing buffer count causes post buffer insertion routing issues. This talk will present techniques to reduce buffer count by combining buffer insertion with gate sizing. We recognize and elegantly deal with the conflicts in size requirements for a gate in optimizing a multitude of interacting timing paths passing through the gate. A number of new ideas are used to extend the traditional bottom-up dynamic algorithm. Several enhancements of the traditional buffer insertion algorithm have also been proposed to reduce memory usage and improve run time. In this talk we will also discuss some recent works developed for faster physical design closure in Oracle, including buffer aware topology generation and row based datapath placement.

Bio: Guo Yu is a senior hardware engineer with Oracle Corp. Austin Design center. He received his PhD in Computer Engineering from Texas A&M University in 2009. In Oracle he has worked on projects including concurrent gate sizing and buffer insertion, row based datapath placement and timing driven buffer aware topology generation.

Host: Dr. Khatri



October 10, 2014
3:55 pm - 5:00 pm