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May 2020

Graduation Recognition Celebration

May 8 @ 6:00 pm - 7:00 pm

What: Graduation Recognition Celebration for Electrical and Computer Engineering Where: Online via YouTube Premieres When: 6 p.m. on Friday, May 8, 2020 More information: See department emails   “CONGRATULATIONS!” – from the Computer Engineering Systems Group's Faculty and Staff !   List of Spring 2020's CEEN Graduates: Graduates Spring 2020 PhD Final Graduates Spring 2020 ME Final Graduates Spring 2020 MS Final

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September 2020

A Full Stack Solution Mitigating Spatial and Temporal Memory Vulnerabilities

September 4 @ 10:40 am - 11:30 am
Free

Dr. Simon Moore University of Cambridge Department of Computer Science and Technology Zoom Link: https://tamu.zoom.us/j/94526994449?pwd=bFdRUHl3RE5DQWFtY25OeFh6WW5NUT09   Abstract: Originally prototyped on MIPS, we have now added CHERI security extensions to the RISC-V ISA, with multiple open-source cores with various microarchitectures prototyped on FPGA. CHERI extensions for RISC-V provide low-level hardware primitives for in-memory capabilities that allows software to dramatically improve security by mitigating many spatial and temporal memory safety vulnerabilities. Spatial vulnerabilities like buffer-overflow and buffer-over read are typically eliminated through the compiler and linker capturing more of the programmer’s original intent. Pointers are mapped into in-memory capabilities that include bounds, permissions and have integrity properties. Temporal memory safety mitigates vulnerabilities like use-after-free through revocation of capabilities, offering a major performance improvement over existing techniques like address sanitiser. Capabilities provide the basis for other software mitigations, including control-flow robustness and highly efficient compartmentalisation.   Biography: Simon Moore is a Professor of Computer Engineering at the University of Cambridge Department of Computer Science and Technology (previously the Computer Laboratory) in England, where he conducts research and teaching in the general area of computer architecture with particular interests in secure and rigorously-engineered processors and subsystems. Robert Watson and Simon Moore lead the CHERI project in Cambridge.              

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Communication-centric Design of Distributed Deep Learning Training Platforms

September 18 @ 10:40 am - 11:30 am
Free

Dr. Tushar Krishna, Asst. Professor Georgia Tech School of Electrical and Computer Engineering (Zoom link below)   Title: Communication-centric Design of Distributed Deep Learning Training Platforms   Abstract: Modern Deep Learning (DL) systems heavily rely on distributed training over high-performance accelerator (e.g., TPU, GPU)-based hardware platforms. Examples today include NVIDIA’s DGX-2, Google’s Cloud TPU and Facebook’s Zion. Efficient DL training on these platforms involves a complex interplay between the DNN model architecture, parallelization strategy, scheduling strategy, collective communication algorithm, network topology, and the accelerator endpoint. In this talk, we present some of our recent efforts towards co-design across this stack. On the compute side, we present the architecture of a GEMM accelerator called SIGMA (HPCA 2020 Best Paper Award) that leverages flexible interconnects within the accelerator to provide extremely high compute utilization for irregular (i.e., non-square) and sparse (i.e., have lot of zeros, ranging from 10-90% during training) GEMMs. Such GEMMs are extremely inefficient to run on current accelerators like NVIDIA tensor cores and Google TPU. Next, we present ASTRA-Sim (ISPASS 2020, HotI 2020), a simulator developed in collaboration with Facebook for studying the SW/HW design-space for Distributed Training. We perform a comparison between Torus (e.g., Google TPU) vs Switch (e.g., NVIDIA DGX-2) topologies for all-reduce and all-to-all collectives, and also study the compute-communication breakdown for training modern DNNs such as ResNet, Transformer and DLRM.   Biography: Tushar Krishna is an Assistant Professor in the School of Electrical and Computer Engineering at Georgia Tech. He also holds the ON Semiconductor Junior Professorship. He has a Ph.D. in Electrical Engineering and Computer Science from MIT (2014), a M.S.E in Electrical Engineering from Princeton University (2009), and a B.Tech in Electrical Engineering from the Indian Institute of Technology (IIT) Delhi (2007). Before joining Georgia Tech in 2015, Dr. Krishna spent a year as a post-doctoral researcher at Intel, Massachusetts. Dr. Krishna’s research spans computer architecture, interconnection networks, networks-on-chip (NoC) and deep learning accelerators - with a focus on optimizing data movement in modern computing systems. Three of his papers have been selected for IEEE Micro’s Top Picks from Computer Architecture, one more received an honorable mention, and three have won best paper awards. He received the National Science Foundation (NSF) CRII award in 2018, a Google Faculty Award in 2019, and a Facebook Faculty Award in 2019 and 2020.   Tushar Krishna     Click for Zoom Link: or: https://tamu.zoom.us/j/94526994449?pwd=RXNqYTRPeG14enFuVTh2N3dzRTJQZz09 Meeting ID: 945 2699 4449; Passcode: Fall2020        

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Efficient Heterogeneous Computing for ML Applications

September 25 @ 10:40 am - 11:30 am
Free

Dr. Eric Liang, Asst. Professor Peking University Department of  Computer Science (Zoom link below)   Title: Efficient Heterogeneous Computing for ML Applications   Abstract: ML applications require high computing power from training phase to inference phase. Heterogeneous systems that couple CPUs with accelerators such as Graphics Processing Units (GPUs) and Field Programmable Gate Arrays (FPGAs) have been employed as the mainstream computing ingredients for AI application systems due to their tremendous computing power and energy efficiency.  In this talk, I will present two chain of works. First, I will introduce our works on accelerating ML applications on FPGAs. Second, I will introduce our works on ML-assisted optimization for heterogeneous system. Biography: Yun (Eric) Liang is currently an associate professor (with tenure) in the department of computer science, Peking University, China. His research focuses on energy-efficient heterogeneous computing, computer architecture, compilation techniques, electronic design automation, and high-level synthesis. He has authored over 90 scientific publications in the premier international journals and conferences in this domain. His research has been recognized by best paper awards at FCCM 2011 and ICCAD 2017 and best paper nominations at PPoPP 2019, DAC 2017, ASPDAC 2016, DAC 2012, FPT 2011, CODES+ISSS 2008. Prof Liang serves as Associate Editor for ACM Transactions in Embedded Computing Systems (TECS) and ACM Transactions on Reconfigurable Technology and Systems (TRETS) and serves in the program committees in the premier conferences in the related domain including (MICRO, ASPLOS, HPCA, DAC, FPGA, FCCM, PACT, CGO, ICCAD, ICS, CC, DATE, CASES, ASPDAC, ICCD)       Click for Zoom Link: or: https://tamu.zoom.us/j/94526994449?pwd=RXNqYTRPeG14enFuVTh2N3dzRTJQZz09 Meeting ID: 945 2699 4449; Passcode: Fall2020      

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October 2020

“Hardware Security for and beyond CMOS Technology”

October 2 @ 10:40 am - 11:30 am
Free

Dr. Johann Knechtel Research Scientist New York University Abu Dhabi, UAE (Zoom link below) Title: Efficient Heterogeneous Computing for ML Applications   Abstract: As with most aspects of electronic systems and integrated circuits, hardware security has raditionally evolved around the dominant CMOS technology. However, with the rise of various emerging technologies, whose main purpose is to overcome the fundamental limitations for scaling and power consumption of CMOS technology, unique opportunities arise also to advance the notion of hardware security. In this talk, I will first outline the various notions of hardware security in general. Next, I will review selected emerging technologies, namely (i) spintronics, (ii) memristors, (iii) carbon nanotubes and transistors, (iv) nanowires and transistors, and (v) 3D and 2.5D integration. I will then discuss their application to advance hardware security and also outline challenges. Biography: Johann Knechtel received the M.Sc. degree in Information Systems Engineering (Dipl.-Ing.) in 2010 and the Ph.D. degree in Computer Engineering (Dr.-Ing., summa cum laude) in 2014, both from TU Dresden, Germany. He is a Research Scientist with New York University Abu Dhabi, United Arab Emirates. From 2015 to 2016, he was a Postdoctoral Researcher with the Masdar Institute of Science and Technology, Abu Dhabi; from 2010 to 2014, he was a Ph.D. Scholar and Member with the DFG Graduate School on “Nano- and Biotechnologies for Packaging of Electronic Systems” hosted at TU Dresden; in 2012, he was a Research Assistant with the Chinese University of Hong Kong, Hong Kong; and in 2010, he was a Visiting Research Student with the University of Michigan at Ann Arbor, MI, USA. His research interests cover VLSI physical design automation, with particular focus on emerging technologies and hardware security. He has (co-)authored around 50 publications. Talking Points: Hardware Security Emerging Technologies Overview on Fundamentals, Applications, and Challenges     Click for Zoom Link: or: https://tamu.zoom.us/j/94526994449?pwd=RXNqYTRPeG14enFuVTh2N3dzRTJQZz09 Meeting ID: 945 2699 4449; Passcode: Fall2020  

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CESG Seminar: “CHiRP: Control-Flow History Reuse Prediction”

October 9 @ 10:40 am - 11:30 am
Free

Elba Garza Dept. of Computer Science Texas A&M University (Zoom link below) Title: CHiRP: Control-Flow History Reuse Prediction   Abstract: Translation Lookaside Buffers (TLBs) play a critical role in hardware-supported memory virtualization. To speed up address translation and reduce costly page table walks, TLBs cache a small number of recently-used virtual-to-physical address translations. TLBs must make the best use of their limited capacities. Thus, TLB entries with low potential for reuse should be replaced by more useful entries. This paper contributes to an aspect of TLB management that has received little attention in the literature: replacement policy. We show how predictive replacement policies can be tailored toward TLBs to reduce miss rates and improve overall performance. We begin by applying recently proposed predictive cache replacement policies to the TLB. We show these policies do not work well without considering specific TLB behavior. Next, we introduce a novel TLB-focused predictive policy, Control-flow History Reuse Prediction (CHiRP). This policy uses a history signature and replacement algorithm that correlates to known TLB behavior, outperforming other policies. For a 1024-entry 8-way set-associative L2 TLB with a 4KB page size, we show that CHiRP reduces misses per 1000 instructions (MPKI) by an average 28.21% over the least-recently- used (LRU) policy, outperforming Static Re-reference Interval Prediction (SRRIP) , Global History Reuse Policy (GHRP) and SHiP , which reduce MPKI by an average of 10.36%, 9.03% and 0.88%, respectively. Biography: Elba Garza is a fifth-year CSCE PhD student working under Daniel A. Jiménez. Her work focuses on making hardware predictive structures & policies (e.g. branch prediction, prefetching, cache replacement) more effective and resilient to evolving computing demands and has been published in top tier computer architecture conferences. After graduation, she hopes to enter academia in a teaching-focused professorial position. Talking Points: - Translation Lookaside Buffer Replacement Policies - Improving Hardware Predictive Structures   Click for Zoom Link: or: https://tamu.zoom.us/j/94526994449?pwd=RXNqYTRPeG14enFuVTh2N3dzRTJQZz09 Meeting ID: 945 2699 4449; Passcode: Fall2020  

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CESG Seminar: Design for Test Applications in System Debug, Resilient Computing and Functional Safety

October 23 @ 10:40 am - 11:30 am
Free

Dr. Wei Li Principal Engineer Intel Austin Design Center (Zoom link below) Title: Design for Test Applications in System Debug, Resilient Computing and Functional Safety Abstract: Design For Test (DFT) architecture such as scan system, array memory test controller and TAP controller have been widely used for the silicon manufacturing screening test to achieve low DPM. Recently these DFT techniques have been expanded to other areas such as system level debug, resilient computing and functional safety. In this talk, we are going to discuss a few such applications. Biography: Dr. Wei Li is a Principal Engineer as well as a design team manager from Intel Austin Design Center where he is responsible for Atom CPU DFT (Design for Testing) DFD (Design for Debug) and Functional Safety features. He received his Ph.D. in ECE from University of Iowa in 2004. He has published 17 papers in both internal and external conferences.  He also has multiple patents in related fields. Talking Points: DFT Architecture Requirements on testing and debugging at system level in the field Applications to address challenges   Click for Zoom Link: or: https://tamu.zoom.us/j/94526994449?pwd=RXNqYTRPeG14enFuVTh2N3dzRTJQZz09 Meeting ID: 945 2699 4449; Passcode: Fall2020  

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CESG Seminar: Hardware-Based Acceleration of Homomorphic Encryption

October 30 @ 10:40 am - 11:30 am
Free

Dr. Michail (Mihalis) Maniatakos Associate Professor in Electrical and Computer Engineering New York University at Abu Dhabi, UAE (Zoom link below) Title: Hardware-Based Acceleration of Homomorphic Encryption Talking Points: - Introduction to homomorphic encryption - Hardware designs for accelerating homomorphic encryption - Architectural support for homomorphic encryption - High-level framework for compiling C++ program with homomorphically encrypted operands Abstract: The rapid expansion and increased popularity of cloud computing comes with no shortage of privacy concerns about outsourcing computation to semi-trusted parties. While cryptography has been successfully used to solve data-in-transit (e.g., HTTPS) and data-at-rest (e.g., AES encrypted hard disks) concerns, data-in-use protection remains unsolved. Homomorphic encryption, the ability to meaningfully manipulate data while data remains encrypted, has emerged as a prominent solution. The performance degradation compared to non-private computation, however, limits its practicality. In this talk, we will discuss our ongoing efforts towards accelerating homomorphic encryption at the hardware level. We will present the first ASIC implementation of a partially homomorphic encrypted co-processor, as well as discuss the prototype of a fully homomorphic encryption accelerator. The talk will also introduce E3, our framework for compiling C++ programs to their homomorphically encrypted counterparts, as well as E3X, our architectural extensions for accelerating computation on encrypted data demonstrated on an OpenRISC architecture. Biography: Michail Maniatakos is an Associate Professor of Electrical and Computer Engineering at New York University Abu Dhabi, UAE, and a Global Network University Associate Professor at the NYU Tandon School of Engineering, USA. He is the Director of the MoMA Laboratory (nyuad.nyu.edu/momalab). He received his Ph.D. in Electrical Engineering, as well as M.Sc., M.Phil. degrees from Yale University, New Haven, CT, USA. He also received the B.Sc. and M.Sc. degrees in Computer Science and Embedded Systems, respectively, from the University of Piraeus, Greece. His research interests, funded by industrial partners, the US government, and the UAE government, include privacy-preserving computation, industrial control systems security, and machine learning security. Prof. Maniatakos has authored several publications in IEEE transactions and conferences, holds patents on privacy-preserving data processing and serves in the technical program committee for various international conferences. His cybersecurity work has also been extensively covered by Reuters and BBC.     Click for Zoom Link: or: https://tamu.zoom.us/j/94526994449?pwd=RXNqYTRPeG14enFuVTh2N3dzRTJQZz09 Meeting ID: 945 2699 4449; Passcode: Fall2020

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November 2020

CESG SEMINAR: 5G Antenna Optimization

November 6 @ 10:40 am - 11:30 am
Free

Dr. Pavlos Lazaridis Professor in Electronic and Electrical Engineering University of Huddersfield, UK (Zoom link below) Title: 5G Antenna Optimization Talking Points: - Evolutionary optimization algorithms - 5G base and mobile antennas - GPU computing   Abstract: Results of several antenna optimizations will be presented using particle swarm optimization (PSO), invasive weed optimization (IWO), and differential evolution (DE) and Nvidia GPUs. 5G base and mobile terminal antenna examples will be briefly presented and the efficiency of algorithms will be assessed. Biography: Dr. Pavlos Lazaridis is a Professor in Electronic and Electrical Engineering at the University of Huddersfield, UK. He received the Electrical Engineering degree from the Aristotle University of Thessaloniki, Greece, in 1990, the MSc. degree in Electronics from Université Pierre et Marie Curie, Paris 6, France, in 1992, and the Ph.D. degree in Electronics and telecommunications from Ecole Nationale Supérieure des Télécommunications (ENST) and Paris 6, Paris, in 1996. From 1991 to 1996, he was involved with research on semiconductor lasers, wave propagation, and nonlinear phenomena in optical fibers for the Centre National d’Etudes des Télécommunications (CNET) and teaching at the ENST. In 1997, he became the Head of the Antennas and Propagation Laboratory, TDF-C2R Metz (Télédiffusion de France/France Télécom Research Center), where he was involved with research on antennas and radio coverage for cellular mobile systems (GSM), Digital Audio Broadcasting (DAB), and Digital Video Broadcasting-Terrestrial (DVB-T). From 1998 to 2002, he was with the European Patent Office, Rijswijk, The Netherlands, as a Senior Examiner in the field of Electronics and Telecommunications. From 2002 to 2014, he was involved with teaching and research at the Alexander Technological Educational Institute of Thessaloniki, Greece, and Brunel University, West London. He is leading the EU Horizon 2020 projects ITN-MOTOR5G and RISE-RECOMBINE for the University of Huddersfield. He is a member of the IET and a senior member of the IEEE.     Click for Zoom Link: or: https://tamu.zoom.us/j/94526994449?pwd=RXNqYTRPeG14enFuVTh2N3dzRTJQZz09 Meeting ID: 945 2699 4449; Passcode: Fall2020

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CESG SEMINAR: A Statistical Distribution-based Deep Neuron Network Model – A New Perspective on Effective Learning

November 20 @ 10:40 am - 11:30 am
Free

Dr. Jinjun Xiong Researcher and Program Director for AI and Hybrid Clouds Systems IBM Thomas J. Watson Research Center (Zoom link below) Title: A Statistical Distribution-based Deep Neuron Network Model – A New Perspective on Effective Learning Talking Points: - Explicit representation of correlated statistical distribution for DNN - Additional dimension for accelerating DNN inferences for real-time throughput and latency   Abstract: The impressive results achieved by deep neural networks (DNNs) in various tasks, computer vision in particular, such as image recognition, object detection and image segmentation, have sparked the recent surging interests in artificial intelligence (AI) from both the industry and academia alike. The wide adoption of DNN models in real-time applications has, however, brought up a need for more effective training of an easily parallelizable DNN model for low latency and high throughput. This is particularly challenging because of DNN's deep structures. To address this challenge, we observe that most existing DNN models operate on deterministic numbers and process one single frame of image at a time, and may not fully utilize the temporal and contextual correlation typically present in multiple channels of the same image or adjacent frames from a video. Based on well-established statistical timing analysis foundations from the EDA domain, we propose a novel statistical distribution-based DNN model that extends existing DNN architectures but operates directly on correlated distributions rather than deterministic numbers. This new perspective of training DNN has resulted in surprising effects on achieving not only improved learning accuracy but also reduced latency and increased high throughputs. Preliminary experimental results on various tasks, including 3D Cardiac Cine MRI segmentation, showed a great potential of this new type of statistical distribution-based DNN model, which warrants further investigation Biography: Dr. Jinjun Xiong is currently Researcher and Program Director for AI and Hybrid Clouds Systems at the IBM Thomas J. Watson Research Center. He co-founded and co-directs the IBM-Illinois Center for Cognitive Computing Systems Research (C3SR.com) with Prof. Wen-mei Hwu at UIUC. His recent research interests are on across-stack AI systems research, which includes AI solutions, algorithms, tooling and computer architectures. Many of his research results have been adopted in IBM’s products and tools. He published more than 100 peer-reviewed papers in top AI conferences and systems conferences. His publication won seven Best Paper Awards and eight Nominations for Best Paper Awards. He also won top awards from various international competitions, including the recent champion for the IEEE GraphChallenge on accelerating sparse neuron networks, and champions for the DAC'19 Systems Design Contest on designing an object detection neural network for edge FPGA and GPU devices.   Click for Zoom Link: or: https://tamu.zoom.us/j/94526994449?pwd=RXNqYTRPeG14enFuVTh2N3dzRTJQZz09 Meeting ID: 945 2699 4449; Passcode: Fall2020

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