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September 2017
Free

CESG Seminar: “Small is the New Big: Data Analytics on the Edge – An overview of processors and algorithms for deep learning techniques on the edge”

September 22 @ 4:10 pm - 5:10 pm
WEB, Room 236-C,
Wisenbaker Engineering Building

Dr. Abhay Samant, Vice President of Engineering Hiller Measurements Title: “Small is the New Big: Data Analytics on the Edge – An overview of processors and algorithms for deep learning techniques on the edge” Abstract: Deep learning techniques are becoming popular as they fuel many Artificial Intelligence enabled systems. One of the key trends that is observed is the transition of these algorithms from the core (such as cloud) to the edge (nodes). Traditionally, deep learning was computationally intensive, so processing on expensive powerful servers was the only option. As the need for moving these algorithms to the edge increases, new hardware architectures are evolving to facilitate this. In this talk, I will present an overview of different hardware architectures and products for edge processing. I will share some initial results from our experiments for implementing real-time machine learning classifiers (a Multi-Layer Perceptron Model) on FPGA and compare it with the Support Vector Machine algorithms. Bio: Dr. Abhay Samant is Vice President of Engineering at Hiller Measurements, where he leads an engineering team working on test and measurement systems for aero/defense, automotive, and semiconductor applications. He is Adjunct Faculty at the McCombs School of Business at UT-Austin. Prior to this, Dr. Samant has worked as Section Manager of RF and wireless communications at National Instruments. He is a senior member of IEEE and has over 20 years of experience in the areas of RF, wireless communications, and signal processing. Abhay has multiple patents in the areas of GPS, WLAN, and signal intelligence. He is co-author of the book, LabVIEW for Signal Processing and has published numerous conference and journal papers. In previous roles, Abhay has served as the Regional Marketing Manager for NI (India, Russia, Arabia), R&D Head for NI-India and has played multiple engineering and management leadership roles at NI R&D in Austin. Abhay received his PhD in Electrical Engineering from the Indian Institute of Technology in 2016, MS in Computer Science from the University of Illinois at Urbana-Champaign in 1996 and his MS in Electrical Engineering from the University of Kentucky at Lexington in 1994. Abhay’s research interests include hybrid, reconfigurable architectures for MAC-PHY technologies for wireless communications, design of cost-effective channel sounding systems, and developing creative technologies for making learning fun. Abhay’s research areas also include application of communication signal processing techniques onto real-time high-performance computing architectures and development of scalable and flexible test-bed architectures for spectrum monitoring, signal intelligence, connected car, and radar applications. Pizza Provided

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Free

CESG SEMINAR: “Systems for Clinical Outcomes Predictions”

September 15 @ 4:10 pm - 5:10 pm
WEB, Room 236-C,
Wisenbaker Engineering Building

Dr. Bobak Mortazavi Texas A & M University Abstract: The design of personal medical embedded systems for user-centric health monitoring involves an understanding of platform development for data collection, applications of machine learning for processing vast quantities of varying data, and an understanding of the underlying clinical questions these systems are trying to address. The interdisciplinary nature of these tasks requires an understanding of the clinical issues being addressed, and then developing specific systems and algorithms to address these, along with the unique challenges posed by each individual application. This talk focuses on an understanding of clinical data, the challenges posed by implementing machine learning techniques, understanding the differences between methods used in clinical outcomes predictions and those available to computer scientists, and then examines several open-ended case studies that have the potential for both algorithmic and embedded systems improvements. Bio: Dr. Bobak Mortazavi is an Assistant Professor in Computer Science and Engineering at Texas A&M. After receiving his bachelor’s degree from the University of California Berkeley, he earned his PhD in Computer Science from the University of California Los Angeles where he focused on the development of embedded systems for the Wireless Health Institute. Most recently, he was a postdoctoral associate, and then instructor, in the department of internal medicine, section of cardiology, at the Yale School of Medicine. He has recently focused on clinical research challenges in predictive models and comparative effectiveness techniques, in order to better address the challenges of personalized health monitoring, in the interest of developing personalized remote systems for clinical outcomes.

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Free

CESG Fishbowl Seminar: “Emerging RRAM Technologies for Computing and Sensing Applications”

September 14 @ 2:30 pm - 3:30 pm

Dr. Baker Mohammad Associate Professor, ECE at Khalifa University, Abu Dhabi, UAE Abstract: Memristor is a type of RRAM that was postulated by Leon Chua in 1971 and was realized as a physical device by HP labs in 2008; this realization spurred a great interest in memristors as a fundamental electronic element. Memristor-based technology is expected to provide much better scalability, higher utilization when used as memory, and overall lower energy consumptions compared to traditional CMOS technology. In addition to utilizing memristor in traditional computing platform, researchers are looking into using MR in Neuromorphic, IN-Memory-Commuting, Hardware accelerator and Sensing applications. The topic of this seminar will highlight the challenges with existing CMOS technology and will focus on emerging memristor RRAM memory technology and the role they may play in future Analog and Digital electronic system design. I will elaborate on my group work in the following areas: 1- Memristor modeling, synthesis and sensing application; 2- In-Memory-Computing using memristor; and 3- Describe the different memristors realized by the group and their potential usage in sensing (radiation, glucose) application. Bio: Dr. Baker Mohammad is currently an Associate Professor at the ECE at Khalifa University and a founding member of Khalifa University Semiconductor Research Center. He is a Senior Member of the IEEE and serves as an editor to the microelectronics journal, Elsevier. Dr. Mohammad earned his PhD from UT at Austin, his M.S. from Arizona State University, Tempe, and BS from the University of New Mexico, Albuquerque, all in ECE. Prior to joining Khalifa University Baker has over 16-years industrial experience working for Intel and Qualcomm in microprocessor design with emphasis on embedded system, memory, and low power design. His research interest includes power efficient computing, high yield embedded memory, emerging technology such as memristor, STTRAM, and computer architecture. In addition, he is engaged in micro-watt range computing platform for WSN focusing on energy harvesting and power management including efficient dc/dc, ac/dc convertors. He authored/co-authored over 90 journals and conference proceedings, 3 books, 18 US patents, Baker Served in many technical committee for IEEE conferences and reviewers for journals including TVLSI, IEEE Circuits and Systems. Baker has extensive experience for attracting and managing research grants. He won many competitive grants including: KUIRF level 2 funding twice, Semiconductor Research Corporation (SRC), ADEC, and UAE Space Agency.

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Free

CESG SEMINAR: “The Rewriting of a 50-Year-Old Solution: The Normalized Singular Value Decomposition of Non-Symmetric Matrices Using Givens Fast Rotations”

September 8 @ 4:10 pm - 5:00 pm
WEB, Room 236-C,
Wisenbaker Engineering Building

Ehsan Rohani Texas A & M University   Abstract: In this presentation, we introduce the algorithm and the fixed point hardware to calculate the normalized singular value decomposition of a non-symmetric matrices using Givens fast (approximate) rotations. This algorithm only uses the basic combinational logic modules such as adders, multiplexers, encoders, Barrel shifters (B-shifters), and comparators and does not use any lookup table. This method in fact combines the iterative properties of singular value decomposition method and CORDIC method in one single iteration. The introduced architecture is a systolic architecture that uses two different types of processors, diagonal and non-diagonal processors. The diagonal processor calculates, transmits and applies the horizontal and vertical rotations, while the non-diagonal processor uses a fully combinational architecture to receive, and apply the rotations. The design presented in this work provides 2.83∼649 times better energy per matrix performance compared to the state of the art designs. Bio: Ehsan Rohani received his B.Sc. with honors in Electronic Engineering from the University of AmirKabir Tehran, Iran. He received his M.Sc. with honors in Electronic Engineering, from the University of Tehran, Iran. Rohani worked on baseband implementation of WiMAX transceiver as his M.Sc. thesis while he was teaching Math, Robotics and Electronics in Tehran schools (2003- 2006). He lectured for undergraduate courses (Electrical Circuits, Electronic Circuits, Logic Circuits, and …) in Islamic Azad University (2006- 2010), and cooperated with Danesh and Honar Institutions (supported by UNICEF). In 2010, Rohani attended the Texas A&M graduate program as a Ph.D. student where he also received the 2015 Outstanding Teaching Assistant Award. Rohani is currently a senior member of VLSI Signal Processing (VLSIP) Lab and he has defended his Ph.D. dissertation on “Hardware Solutions for Next Generation of Telecommunication Systems Physical Layer Implementation.” in December 2016. Rohani’s research interests lie in the area of baseband modeling and implementation of digital communication systems, digital signal processing, bit-true model extraction of digital circuits, computer arithmetic, hardware and software implementation, system simulation, digital filter design, low power techniques for VLSI circuits and DSPs, circuit level design of digital circuits and hardware simulation and implementation of digital systems.

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August 2017
Free

CESG Fishbowl Seminar: Distributed Control of Large-Scale Infrastructure Networks

August 11 @ 1:30 pm - 2:30 pm

Sivaranjani Seetharaman Graduate student, Dept. of Electrical Engineering University of Notre Dame Abstract: With the proposed development of smart cities around the world, research into novel scalable control techniques for large-scale infrastructure networks is becoming increasingly important. The first half of this talk will focus on disturbance management in networked systems by exploiting integrated communication infrastructure. It will be demonstrated that localization and attenuation of disturbances in distributed systems can be achieved by communicating information about the disturbance faster than its speed of propagation through the network. The role of communication delays and packet drops on disturbance localization will also be explored. In the second half of this talk, scalable dissipativity and passivity based control techniques for large-scale interconnected systems, specifically power grids, will be discussed. The modeling of a smart grid with distributed generation as a parameter varying system with passivity violations and the derivation of control designs that ensure stability and improve the performance of this system will be presented. This talk will also provide a brief overview of the research carried out in the Distributed Systems Lab at the University of Notre Dame. Bio: Sivaranjani Seetharaman is a graduate student in the Department of Electrical Engineering, University of Notre Dame. She obtained her undergraduate and Master’s degrees, both in electrical engineering, from the PES Institute of Technology, India and the Indian Institute of Science, India in 2011 and 2013 respectively. During 2011-2013, she was also an intern in the Electromechanical Control Systems lab at GE Global Research, Bangalore. Sivaranjani’s research interests are in the area of distributed control for large-scale infrastructure networks, with emphasis on power grids and transportation networks. She is a recipient of the prestigious and selective international Schlumberger Foundation Faculty for the Future fellowship and the Zonta International Amelia Earhart fellowship. She is also a Notre Dame NSF Ethical Leaders in STEM fellow for the year 2016-17. Host: Le Xie

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Free

CESG: Distributed Algorithms for Cyberphysical Systems

August 10 @ 2:30 pm - 4:00 pm

Abstract Cyberphysical Systems (CPS) are very large networks in which collaborating agents possessing sensing, communication and computation capabilities are interconnected for controlling physical entities. Applications are ubiquitous in sensor networks, robotics, transportation, and smart grids. In this talk, I will present distributed, asynchronous and real-time algorithms for CPS, and illustrate applications in transportation, robotics and cyber security of CPS. In specific: a) Distributed optimization: We propose a new block-coordinate operator splitting method that can handle a wide range of problems in multi-agent systems, signal processing and machine learning. We establish exponential convergence under a certain metric subregularity condition (which is weaker than strong convexity). We proceed to develop randomized distributed methods for multi-agent optimization, and exhibit our methods in the context of Network Utility Maximization and Distributed Model Predictive Control. On another front, we propose a novel exponentially converging gossip algorithm for GPS-free multi-agent localization. b) Travel time estimation: We propose and analyze a method for performing compressed sensing on an infinite data stream. Our protocol involves a) encoding, via compressively sampling sliding windows of the data stream, and b) decoding, by means of solving LASSO using a newly developed quasi-Newton proximal method with accelerated convergence rates. We apply our framework to the problem of sparse kernel density estimation, and delineate its advantages for adaptively learning travel time distributions in transportation networks in real-time. c) Cyber Security: We establish fundamental asymptotic bounds on the security of distributed protocols to collusion attacks. Our analysis enacts an encouraging result, in that the number of attackers that can be tolerated in large-scale CPS is ‘almost linear’ in the number of benign agents. Furthermore, we propose a theme for performing computations directly on encrypted data in a distributed fashion, and discuss its implications in the realm of secure cloud computing. Bio: Nick Freris is an assistant professor of Electrical and Computer Engineering at New York University Abu Dhabi (NYUAD), and a Global Network Assistant Professor at New York University Tandon School of Engineering. He is the director of Cyberphysical Systems Laboratory (CPSLab) at NYUAD, and a member of the Center for Cyber Security (CCS). He received the Diploma in Electrical and Computer Engineering from the National Technical University of Athens (NTUA), Greece in 2005, and the M.S. degree in Electrical and Computer Engineering, the M.S. degree in Mathematics, and the Ph.D. degree in Electrical and Computer Engineering all from the University of Illinois at Urbana-Champaign in 2007, 2008, and 2010, respectively. Dr. Freris’s research interests lie in the area of cyberphysical systems: distributed estimation, optimization and control, data mining/machine learning, cyber security, and applications in transportation, sensor networks and robotics. His research was recognized with the 2014 IBM High Value Patent award, two IBM invention achievement awards, and the Gerondelis foundation award. Previously, Dr. Freris was a senior researcher in the School of Computer and Communication Sciences at École Polytechnique Fédérale de Lausanne (EPFL), Switzerland, from 2012-2014, and a postdoctoral researcher in IBM Research – Zurich, Switzerland, from 2010-2012. Dr. Freris is a senior…

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Free

CESG Seminar: Abstraction and applied mathematics: functional analysis in the 20th century

August 8 @ 4:00 pm - 5:00 pm

Join CESG and Prof. Seidman for some comments (primarily historical) on how we now think of Des and how Functional Analysis provides the essential framework for one to work with applications. Professor Thomas Seidman Department of Mathematics and Statistics University of Maryland, Baltimore County (UMBC) Host: P.R. Kumar

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May 2017
Free

GENI Regional Workshop and Camp

May 22 @ 8:00 am - May 26 @ 1:00 pm
Emerging Technologies Bldg.,
101 Bizzell St. College Station, TX 77843
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More info: tx.ag/GENI Texas A&M University will be hosting the National Science Foundation’s (NSF) Global Environment for Network Innovations (GENI) regional workshop and camp, May 22-26, 2017. GENI provides a virtual laboratory for networking and distributed systems research and education. It is well-suited for exploring networks at scale, thereby promoting innovations in network science, security, services and applications. Highlights of the event include 5G cellular networks and software-defined networking.  The workshop and the camp will offer an opportunity to learn about GENI and how you can use it for your education and research needs. GRW will begin on Monday, May 22. And, the camp will continue through Friday, May 26. Please mark your calendar, and find details at tx.ag/GENI. The GRW agenda includes keynotes by two prominent researchers: – Professor Henning Schulzrinne, Columbia University & – Professor Lin Zhong, Rice University. Registration is free. Organizers: Dr. Alex Sprintson Dr. Walt Magnussen

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Free

CESG Fishbowl Seminar: “Latency Analysis for Distributed Storage”

May 11 @ 2:30 pm - 3:30 pm

Prof. Parimal Parag, Dept. of ECE, Indian Institute of Science Abstract: Modern communication and computation systems consist of large networks of unreliable nodes. Yet, it is well known that such systems can provide aggregate reliability via information redundancy, duplicating paths, or replicating computations. While redundancy may increase the load on a system, it can also lead to major performance improvements through the judicious management of additional system resources. Two important examples of this abstract paradigm are content access from multiple caches in content delivery networks and master/slave computations on compute clusters. Many recent works in the area have proposed bounds on the latency performance of redundant systems, characterizing the latency-redundancy trade-off under specific load profiles. Following a similar line of research, this work introduces new analytical bounds and approximation techniques for the latency-redundancy trade-off for a range of system loads and two popular redundancy schemes. The proposed framework allows for approximating the equilibrium latency distribution, from which various metrics can be derived including mean, variance, and the tail decay of stationary distributions. Bio: Parimal Parag is currently an assistant professor in the department of electrical communication engineering at the Indian Institute of Science at Bangalore. He was working as senior systems engineer in R&D at ASSIA Inc. from October 2011 to November 2014. He received his B. Tech. and M. Tech. degrees from Indian Institute of Technology Madras in Fall 2004; and PhD degree from Texas A&M University in Fall 2011. He was at Stanford University and Los Alamos National Laboratory, in the autumn of 2010 and summer of 2007, respectively. He conducts research in network theory, applied probability, optimization methods, and in their applications to distributed systems. His previous work includes performance evaluation, monitoring, and control of large broadband communication systems and networks.   Free: Snacks & Drinks

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Free

CESG Seminar: “Trustworthy Integrated Circuit Design”

May 5 @ 11:30 am - 12:30 pm
WEB, Room 236-C,
Wisenbaker Engineering Building
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“Trustworthy Integrated Circuit Design” Abstract: Designers use third-party intellectual property (IP) cores and outsource various steps in their integrated circuit (IC) design and manufacturing flow. As a result, security vulnerabilities have been emerging, forcing IC designers and end users to reevaluate their trust in ICs. If an attacker gets hold of an unprotected IC, attacks such as reverse-engineering the IC and piracy are possible. Similarly, if an attacker gets hold of an unprotected design, insertion of malicious circuits in the design and IP piracy are possible. To thwart these and similar attacks, we have developed three defenses: IC camouflaging, logic encryption, and split manufacturing. IC camouflaging modifies the layout of certain gates in the IC to deceive attackers into obtaining an incorrect netlist, thereby, preventing reverse engineering by a malicious user. Logic encryption implements a built-in locking mechanism on ICs to prevent reverse engineering and IP piracy by a malicious foundry and user.  Split manufacturing splits the layout and manufactures different metal layers in two separate foundries to prevent reverse engineering and piracy by a malicious foundry. We then describe how these techniques are enhanced by using provably-secure techniques thereby leading to trustworthy ICs. Bio: Jeyavijayan (JV) Rajendran is an Assistant Professor in the Department of Electrical and Computer Engineering at the University of Texas at Dallas. He obtained his Ph.D. degree in the Electrical and Computer Engineering Department at New York University in August 2015. His research interests include hardware security and emerging technologies. His research has won the NSF CAREER Award in 2017, the ACM SIGDA Outstanding Ph.D. Dissertation Award in 2017, and the Alexander Hessel Award for the Best Ph.D. Dissertation in the Electrical and Computer Engineering Department at NYU in 2016. He has won three Student Paper Awards (ACM CCS 2013, IEEE DFTS 2013, and IEEE VLSI Design 2012); four ACM Student Research Competition Awards (DAC 2012, ICCAD 2013, DAC 2014, and the Grand Finals 2013); Service Recognition Award from Intel; Third place at Kaspersky American Cup, 2011; and Myron M. Rosenthal Award for Best Academic Performance in M.S. from NYU, 2011. He organizes the annual Embedded Security Challenge, a red-team/blue-team hardware security competition and has co-founded Hack@DAC, a student security competition co-located with DAC. He is a member of IEEE and ACM.   FREE SNACKS

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