**Journal Articles:**

** Computational Neuroscience**

1. **B. Yan**, P. Li, “The emergence of abnormal hypersynchronization in the anatomical structural network of human brain”, **NeuroImage**, 66(15), pp.34-61, Jan. 2013.

2. Y. Zhang, **B. Yan**, M. Wang, J. Hu, H.Lu, P.Li, “Linking brain behavior to underlying cellular mechanisms via large-scale brain modeling and simulation”, **Neurocomputing**, 97(15), pp.317-331, Nov. 2012.

3. **B. Yan**, P. Li, “An integrative view of mechanisms underlying generalized spike-and-wave epileptic seizures and its implication on optimal therapeutic treatments”, **PLoS ONE**, 6(7): e22440, pp.1-20, July 2011.

4. **B. Yan**, P. Li, “Reduced order modeling of passive and quasi-active dendrites for nervous system simulation”, Journal of Computational Neuroscience (**JCNS**), 31(2): pp.247-271, Oct. 2011.

**Modeling and Simulation of Dynamical Systems, and Computer-Aided Design of VLSI**

5. S. Lai,** B. Yan**, P. Li, “Localized stability checking and design of IC power delivery with distributed voltage regulators”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (**TCAD**), vol.32, no.9, pp.1321-1334, September 2013.

6. **B. Yan**, S. X.-D. Tan, L. Zhou, J. Chen, R. Shen, “Decentralized and passive model reduction of linear networks with massive ports”, IEEE Transactions on Very Large Scale Integrated Systems (**TVLSI**), vol.20, no.5, pp.865-877, May 2012.

7. **B. Yan**, S. X.-D. Tan, J. Fan, “Passive rational interpolation based reduction via Caratheodory extension for general systems”, IEEE Transactions on Circuits and Systems II (**TCAS II**) , vol.57, no.9, pp.750-755, September 2010.

8. S. X.-D. Tan, **B. Yan, **H. Wang, “Recent advance in non-Krylov subspace model order reduction of interconnect circuits”, Tsinghua Science & Technology, vol.15, no.2, pp. 151-168, April 2010 (**invited**).

9. N. Mi, S. X.-D. Tan, **B. Yan**, “Multiple block structure-preserving reduced order modeling of interconnect circuits”, Integration, The VLSI Journal, vol.42, no.2, pp.158-168, Feb. 2009.

10. **B. Yan**, S. X.-D. Tan, B. McGaughy, “Second-order balanced truncation for passive order reduction of RLCK circuits”, IEEE Transactions on Circuits and Systems II (**TCAS II**), vol.55, no.9, pp.942-946, September 2008.

11. P. Liu, S. X.-D. Tan, **B. Yan**, B. McGaughy, “An efficient terminal and model order reduction algorithm”, Integration, The VLSI Journal, vol.41, no.2, pp.210-218, Feb. 2008.

**Conference Proceedings:**

**Computational Neuroscience**

1.** **M. Wang, **B. Yan**, J. Hu, P. Li, “Large-scale simulation of neural networks with biophysically accurate models on graphics processors”, Proceedings of IEEE International Joint Conference on Neural Networks (**IJCNN’11**), pp.3184-3193, San Jose, CA, July 2011.

**Modeling and Simulation of Dynamical Systems, and Computer-Aided Design of VLSI**

2. S. Lai,** B. Yan**, P. Li, “Stability assurance and design optimization of large power delivery networks with multiple on-chip voltage regulators”, Proceedings of IEEE/ACM 2012 International Conference on Computer-Aided Design (**ICCAD’12)**, pp.247-254, San Jose, CA, November 2012 (24% acceptance rate)(**IEEE/ACM William J. McCalla Best Paper Award, 1 out of 338 submissions, 0.3%**).

3.** **T. Xu, P. Li,** B. Yan**, “Decoupling for power gating: sources of power noise and design strategies”, Proceedings of 48^{th} IEEE/ACM Design Automation Conference (**DAC’11**), pp.1002-1007,San Diego,CA, June 2011 (22% acceptance rate).

4.** **S. X.-D. Tan, H. Wang, **B. Yan**, “UiMOR-UC Riverside model order reduction tool for post-layout wideband interconnect modeling”, Proceedings of 10^{th} IEEE International Conference on Solid-State and Integrated-Circuit Technology (**ICSICT’10**), pp.1769-1773, Shanghai, China, November 2010 (**invited**)**.**

5. **B. Yan**, S. X.-D. Tan, G. Chen, Y. Cai, “Efficient model reduction of interconnects via double gramians approximation”, Proceedings of 15^{th} IEEE/ACM Asia South Pacific Design Automation Conference (**ASP-DAC’10**), pp.25-30, Taipei, Taiwan, January 2010 (35% acceptance rate).

6.** B. Yan**, S. X.-D. Tan, G. Chen, L. Wu, “Modeling and simulation for on-chip power grid networks by locally dominant Krylov subspace method”, Proceedings of IEEE/ACM 2008 International Conference on Computer-Aided Design (**ICCAD’08**), pp.744-749, San Jose, CA, November 2008 (27% acceptance rate).

7.** B. Yan**, H. Wang, S. X.-D. Tan, “A survey of RLCK reduction and simulation methods by fast truncated balanced realization”, Proceedings of 9^{th} IEEE International Conference on Solid-State and Integrated-Circuit Technology (**ICSICT’08**), pp.2236-2239, Beijing, China, October 2008 (**invited**).

8.** B. Yan**, L. Zhou, S. X.-D. Tan, J. Chen, “DeMOR: Decentralized model order reduction of linear networks with massive ports”, Proceedings of 45^{th} IEEE/ACM Design Automation Conference (**DAC’08**), pp.409-414,Anaheim,CA, June 2008 (23% acceptance rate).

9.** B. Yan**, S. X.-D. Tan, P. Liu, B .McGaughy, “SBPOR: Second-order balanced truncation for passive order reduction of RLC circuits”, Proceedings of 44^{th} IEEE/ACM Design Automation Conference (**DAC’07**), pp.158-161,San Diego,CA, June 2007 (23% acceptance rate).

10. **B. Yan**, P. Liu, S. X.-D. Tan, B. McGaughy, “Passive modeling of interconnects by waveform shaping”, Proceedings of 8^{th }IEEE International Symposium on Quality Electronic Design (**ISQED’07**), pp.356-361,San Jose,CA, March 2007 (33% acceptance rate).

11. N. Mi, **B. Yan**, S. X.-D. Tan, H. Yu, “General block structure-preserving reduced order modeling of interconnect circuits”, Proceedings of 8^{th} IEEE International Symposium on Quality Electronic Design (**ISQED’07**), pp.633-638,San Jose,CA, March 2007 (33% acceptance rate).

12. **B. Yan**, S. X.-D. Tan, P. Liu, “Passive interconnect macromodeling via balanced truncation of linear systems in descriptor form”, Proceedings of 12^{th} IEEE/ACM Asia South Pacific Design Automation Conference (**ASP-DAC’07**), pp.355-360,Yokohama City,Japan, January 2007 (32% acceptance rate).

13. P. Liu, S. X.-D. Tan, **B. Yan**, B. McGaughy, “An extended SVD-based terminal and model order reduction algorithm”, Proceedings of * *IEEE 2006 International Workshop on Behavioral Modeling and Simulation (**BMAS’06**), pp.44-49, San Jose, CA, September 2006.

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