Jiang Hu

Fall 2002, ELEN 689-612: Optimization Techniques for VLSI CAD

Fall 2003, ELEN 689-603: VLSI Circuit Modeling and Optimization

Spring 2005, ELEN 689-607: VLSI Interconnect Modeling and Optimization

Spring 2006, ELEN 689-605: Layout Optimization for Robust VLSI Circuits

Fall 2006, ELEN 475: Introduction to VLSI System Design

Spring 2007, ELEN 689-609: VLSI Design for Manufacturability

Spring 2007, ELEN 468: Advanced Logic Design

Spring 2008, ECEN 689-603: Robust VLSI Design

Fall 2008, ECEN 689-605: Algorithms and Methodologies for VLSI Design

Summer 2009, ECEN 350: Computer Architecture and Design

Fall 2009, ECEN 687/489-504: VLSI Design Automation

Spring 2010, ECEN 454: Digital Integrated Circuit Design

Spring 2010, ECEN 689-608: VLSI System Synthesis

Spring 2011, ECEN 454: Digital Integrated Circuit Design

Summer 2011, ECEN 248: Introduction to Digital Systems Design

Fall 2011, ECEN 454: Digital Integrated Circuit Design

Spring 2012, ECEN 468: Advanced Logic Design

Fall 2012, ECEN 689-602: Optimization and Verification of VLSI Systems

Spring 2013, ECEN 468: Advanced Logic Design

Fall 2013, ECEN 681-604: Computer Engineering and Systems Group Seminar

Fall 2013, ECEN 248: Introduction to Digital Systems Design

Spring 2014, ECEN 468: Advanced Logic Design

Spring 2014, ECEN 687: Introduction to VLSI Design Automation

Fall 2014, ECEN 248: Introduction to Digital Systems Design

Fall 2014, ECEN 350: Computer Architecture and Design

Spring 2015, ECEN 468: Advanced Digital System Design

Spring 2015, ECEN 689-602: Optimization and Verification of Embedded Systems

Fall 2015, ECEN 468: Advanced Digital System Design

Fall 2015, ECEN 687: Introduction to VLSI Design Automation

Fall 2016, ECEN 449/749: Microprocessor System Design

Spring 2017, ECEN 468: Advanced Digital System Design

Spring 2017, ECEN 689-600: Dependable and Autonomic Computing

Fall 2017, ECEN 687: Introduction to VLSI Design Automation

Spring 2018, ECEN 468: Advanced Digital System Design

Fall 2018, ECEN 689-605(700): Dependable Learning Systems

Spring 2019, ECEN 468:Advanced Digital System Design

Fall 2019, ECEN 687: Introduction to VLSI Design Automation

Spring 2020, ECEN 468: Advanced Digital System Design

Fall 2020, ECEN 687: Introduction to VLSI Design Automation

Spring 2021, ECEN 489/689 FPGA Information Processing Systems

Fall 2021, ECEN/CSCE 689: Introduction to Formal Verification

Spring 2022, ECEN 489/689: FPGA Information Processing Systems

Spring 2023, ECEN 468/719: Advanced Digital System Design

Fall 2023, ECEN 687: Introduction to VLSI Design Automation

Spring 2024, ECEN 722: FPGA Information Processing Systems

Please be aware that all papers are copyrighted by the organization responsible for the corresponding conference or journal.

• J. Hu and S. S. Sapatnekar, “Non-Hanan optimization for global VLSI interconnect,” in Layout Optimization in VLSI Designs, B. Lu, D.-Z. Du and S. S. Sapatnekar, ed., Kluwer Academic Publishers, Boston, MA, pp. 89-123, 2002.
• J. Hu, G. Robins and C. N. Sze, “Timing-driven interconnect synthesis,” in Handbook of Algorithms for Physical Design Automation, C. J. Alpert, D. P. Mehta and S. S. Sapatnekar, ed., Auerbach Publications, Taylor & Francis Group, Boca Raton, FL, pp. 509-534, 2009.
• J. Hu, Z. Li and S. Hu, “Buffer insertion basics,” in Handbook of Algorithms for Physical Design Automation, C. J. Alpert, D. P. Mehta and S. S. Sapatnekar, ed., Auerbach Publications, Taylor & Francis Group, Boca Raton, FL, pp. 535-556, 2009.
• J. Hu and C. N. Sze, “Buffering in the layout environment,” in Handbook of Algorithms for Physical Design Automation, C. J. Alpert, D. P. Mehta and S. S. Sapatnekar, ed., Auerbach Publications, Taylor & Francis Group, Boca Raton, FL, pp. 569-584, 2009.
• S. Held and J. Hu, “Gate Sizing,” in Electronic Design Automation for IC Implementation, Circuit Design and Process Technology, 2nd Edition, L. Lavagno, G. Martin, I. Markov, and L. Scheffer, CRC Press, 2016.
• D. Sengupta, J. Hu and S. S. Sapatnekar, “Error Analysis and Optimization in Approximate Arithmetic Circuits,” in Approximate Circuits: Methodologies and CAD, S. Reda and M. Shafique, ed., Springer International Publishing, 2019.
• N. G. Jayasankaran, A. Sanabria-Borbón, E. Sánchez-Sinencio, J. Hu, and J. Rajendran, “Analog IP Protection and Evaluation,” in Emerging Topics in Hardware Security, M. Tehranipoor, ed., Springer International Publishing, 2021.
• H. Ren and J. Hu, Machine Learning Applications in Electronic Design Automation, Springer, 2022.

1. H. Hou, J. Hu and S. S. Sapatnekar, “NonHanan routing,” IEEE Trans. Computer-Aided Design, Vol. 18, No. 4, pp. 436-444, April 1999.
2. J. Hu and S. S. Sapatnekar, “Algorithms for non-Hanan-based optimization for VLSI interconnect under a higher order AWE model,” IEEE Trans. Computer-Aided Design, Vol. 19, No. 4, pp. 446-458, April 2000.
3. C. J. Alpert, G. Gandham, J. Hu, J. L. Neves, S. T. Quay and S. S. Sapatnekar, “Steiner tree optimization for buffers, blockages and bays,” IEEE Trans. Computer-Aided Design, Vol. 20, No. 4, pp. 556-562, April 2001.
4. J. Hu and S. S. Sapatnekar, “A survey on multi-net global routing for integrated circuits,” Integration: The VLSI Journal, Vol. 31, No. 1, pp. 1-49, November 2001. (Invited paper)
5. C. J. Alpert, G. Gandham, M. Hrkic, J. Hu, A. B. Kahng, J. Lillis, B. Liu, S. T. Quay, S. S. Sapatnekar and A. J. Sullivan, “Buffered Steiner trees for difficult instances,” IEEE Trans. Computer-Aided Design, Vol. 21, No. 1, pp. 3-14, January 2002.
6. J. Hu and S. S. Sapatnekar, “Performance driven global routing through gradual refinement,” The VLSI Design Journal, Vol. 15, No. 3, pp. 595-604, 2002.
7. J. Hu and S. S. Sapatnekar, “A timing-constrained simultaneous global routing algorithm,” IEEE Trans. Computer-Aided Design, Vol. 21, No. 9, pp. 1025-1036, September 2002.
8. J. Hu, C. J. Alpert, S. T. Quay and G. Gandham, “Buffer insertion with adaptive blockage avoidance”, IEEE Trans. Computer-Aided Design, Vol. 22, No. 4, pp. 492-498, April 2003.
9. C. J. Alpert, J. Hu, S. S. Sapatnekar and P. G. Villarrubia, “A practical methodology for early buffer and wire resource allocation,” IEEE Trans. Computer-Aided Design, Vol. 22, No. 5, pp. 573-583, May 2003.
10. C. J. Alpert, C. Chu, G. Gandham, M. Hrkic, J. Hu, C. Kashyap and S. T. Quay, “Simultaneous driver sizing and buffer insertion using a delay penalty estimation technique,” IEEE Trans. Computer-Aided Design, Vol. 23, No. 1, pp. 136-141, January 2004.
11. C. J. Alpert, G. Gandham, M. Hrkic, J. Hu, S. T. Quay and C. N. Sze, “Porosity-aware buffered Steiner tree construction,” IEEE Trans. Computer-Aided Design, Vol. 23, No. 4, pp. 517-526, April 2004.
12. H. Su, J. Hu, S. S. Sapatnekar and S. R. Nassif, “A methodology for the simultaneous design of supply and signal networks,” IEEE Trans. Computer-Aided Design, Vol. 23, No. 12, pp. 1614-1624, December 2004.
13. R. Chaturvedi and J. Hu, “An efficient merging scheme for prescribed skew clock routing,” IEEE Trans. VLSI Systems, Vol. 13, No. 6, pp. 750-754, June 2005.
14. Y. Lu, C. N. Sze, X. Hong, Q. Zhou, Y. Cai, L. Huang and J. Hu, “Navigating register placement for low power clock network design,” IEICE Transactions, Vol. E88-A, No. 12, pp. 3405-3411, December 2005.
15. D. Wu, J. Hu and R. Mahapatra, “Antenna avoidance in layer assignment,” IEEE Trans. Computer-Aided Design, Vol. 25, No. 4, pp. 734-748, April 2006.
16. C. J. Alpert, J. Hu, S. S. Sapatnekar and C.-N. Sze, “Accurate estimation of global buffer delay within a floorplan,” IEEE Trans. Computer-Aided Design, Vol. 25, No. 6, pp. 1140-1145, June 2006.
17. A. Rajaram, J. Hu and R. Mahapatra, “Reducing clock skew variability via cross links,” IEEE Trans. Computer-Aided Design, Vol. 25, No. 6, pp. 1176-1182, June 2006.
18. A. Rajaram, B. Lu, J. Hu, R. Mahapatra and W. Guo, “Analytical bound for unwanted clock skew due to wire width variation,” IEEE Trans. Computer-Aided Design, Vol. 25, No. 9, pp. 1869-1876, September 2006.
19. G. Venkataraman, J. Hu and F. Liu, “Integrated placement and skew optimization for rotary clocking,” IEEE Trans. VLSI Systems, Vol. 15, No. 2, pp. 149-158, February 2007.
20. B.-Y. Su, Y.-W. Chang and J. Hu, “An exact jumper insertion algorithm for antenna violation/fixing considering routing obstacles,” IEEE Trans. Computer-Aided Design, Vol. 26, No. 4, pp. 719-733, April 2007.
21. C.-N. Sze, C. J. Alpert, J. Hu and W. Shi, “Path based buffer insertion,” IEEE Trans. Computer-Aided Design, Vol. 26, No. 7, pp. 1346-1355, July 2007.
22. S. Hu, Q. Li, J. Hu and P. Li, “Utilizing redundancy for timing critical interconnect,” IEEE Trans. VLSI Systems, Vol. 15, No. 10, pp. 1067-1080, October 2007.
23. S. Hu, C. J. Alpert, J. Hu, S. Karandikar, Z. Li, W. Shi and C. N. Sze, “Fast algorithms for slew constrained minimum cost buffering,” IEEE Trans. Computer-Aided Design, Vol. 26, No. 11, pp. 2009-2022, November 2007.
24. K. Cao, J. Hu and M. Cheng, “Wire sizing and spacing for lithographic printability and timing optimization,” IEEE Trans. VLSI Systems, Vol. 15, No. 12, pp. 1332-1340, December 2007.
25. K. Cao and J. Hu, “ASIC design flow considering lithography-induced effects,” IET Circuits, Devices and Systems, Vol. 2, No. 1, pp. 23-29, February 2008.
26. C. Zhuo, J. Hu, M. Zhao and K. Chen, “Power grid analysis and optimization using algebraic multigrid,” IEEE Trans. Computer-Aided Design, Vol. 27, No. 4, pp. 738-751, April 2008.
27. W. Shen, Y. Cai, X. Hong, J. Hu and B. Lu, “Zero skew clock routing in X-architecture based on an improved greedy matching algorithm,” Integration, the VLSI Journal, Vol. 41, No. 3, pp. 426-438, May 2008.
28. U. Padmanabhan, J. M. Wang and J. Hu, “Robust clock tree routing in the presence of process variations,” IEEE Trans. Computer-Aided Design, Vol. 27, No. 8, pp. 1385-1397, August 2008.
29. Y. Liu, J. Hu and W. Shi, “Buffering interconnect for multicore processor designs,” IEEE Trans. Computer-Aided Design, Vol. 27, No. 12, pp. 2183-2196, December 2008.
30. Y. Liu, T. Zhang and J. Hu, “Design of voltage overscaled low-power Trellis decoders in presence of process variations,” IEEE Trans. VLSI Systems, Vol. 17, No. 3, pp. 439-443, March 2009.
31. S. Hu, M. Ketkar and J. Hu, “Gate sizing for cell-library-based designs,” IEEE Trans. Computer-Aided Design, Vol. 28, No. 6, pp. 818-825, June 2009.
32. R. Samanta, G. Venkataraman and J. Hu, “Clock buffer polarity assignment for power noise reduction,” IEEE Trans. VLSI Systems, Vol. 17, No. 6, pp. 770-780, June 2009.
33. G. Venkataraman, Z. Feng, J. Hu and P. Li, “Combinatorial algorithms for fast clock mesh optimization,” IEEE Trans. VLSI Systems, Vol. 18, No. 1, pp. 131-141, January 2010.
34. Y. Liu and J. Hu, “A new algorithm for simultaneous gate sizing and threshold voltage assignment,” IEEE Trans. Computer-Aided Design, Vol. 29, No. 2, pp. 223-234, February 2010.
35. S. Hu, P. Shah and J. Hu, “Pattern sensitive placement perturbation for manufacturability,” IEEE Trans. VLSI Systems, Vol. 18, No. 6, pp. 1002-1006, June 2010.
36. R. Samanta, J. Hu and P. Li, “Discrete buffer and wire sizing for link-based non-tree clock networks,” IEEE Trans. VLSI Systems, Vol. 18, No. 7, pp. 1025-1035, July 2010.
37. X. Ye, P. Li, M. Zhao, R. Panda and J. Hu, “Scalable analysis of mesh-based clock distribution networks using application-specific reduced order modeling,” IEEE Trans. Computer-Aided Design, Vol. 29, No. 9, pp. 1342-1353, September 2010.
38. W. Shen, Y. Cai, X. Hong and J. Hu, “An effective gated clock tree design based on activity and register aware placement,” IEEE Trans. VLSI Systems, Vol. 18, No. 12, pp. 1639-1648, December 2010.
39. M. A. R. Chaudhry, Z. Asad, A. Sprintson and J. Hu, “Efficient congestion mitigation using congestion-aware Steiner trees and network coding topologies,” VLSI Design Journal, Vol. 2011, January 2011.
40. Y. Liu, R. Shelar and J. Hu, “Simultaneous technology mapping and placement for delay minimization,” IEEE Trans. Computer-Aided Design, Vol. 30, No. 3, pp. 416-426, March 2011.
41. Y. Liu and J. Hu, “GPU-based parallelization for fast circuit optimization,” ACM Trans. Design Automation of Electronic Systems, Vol. 16, No. 3, pp. 24:1-14, June 2011.
42. M. Ozdal, S. Burns and J. Hu, “Algorithms for gate sizing and device parameter selection for high-performance designs,” IEEE Trans. Computer-Aided Design, Vol. 31, No. 10, pp. 1558-1571, October 2012.
43. X. Chen, J. Hu and N. Xu, “Regularity-constrained floorplanning for multi-core processors,” Integration: the VLSI Journal, Vol. 47, No. 1, pp. 86-95, January 2013.
44. K.-N. Shim, J. Hu and J. Silva-Martinez, “Dual-level adaptive supply voltage system for variation resilience,” IEEE Trans. VLSI Systems, Vol.21, No. 6, pp. 1041-1052, June 2013.
45. K.-N. Shim and J. Hu, “Boostable repeater design for variation resilience in VLSI interconnects,” IEEE Trans. VLSI Systems, Vol. 21, No. 9, pp. 1619-1631, September 2013.
46. X. Chen, Z. Xu, H. Kim, P. Gratz, J. Hu, M. Kishinevsky and U. Ogras, “In-network monitoring and control policy for DVFS of CMP networks-on-chip and last level caches,”ACM Trans. Design Automation of Electronic Systems, Vol. 18, No. 4, October 2013.
47. J.-Y. Won, H. Ryu, T. Debruck, J. Lee and J. Hu, “Proximity sensing based on dynamic vision sensor for mobile devices,” IEEE Trans. Industrial Electronics, Vol. 62, No. 1, pp. 536-544, July 2014.
48. J.-Y. Won, P. Gratz, S. Shakkottai and J. Hu, “Resource sharing centric dynamic voltage and frequency scaling for CMP cores, uncore, and memory,” ACM Trans. Design Automation of Electronic Systems, Vol. 21, No. 4, May 2016.
49. Y. Wang, P. Chen, J. Hu, G. Li and J. Rajendran, “The Cat and Mouse in Split Manufacturing,” IEEE Transactions on VLSI Systems, Vol. 26, No. 5, May 2018.
50. W. Xu, S. Sapatnekar and J. Hu, “A Simple Yet Efficient Accuracy-Configurable Adder Design,” IEEE Transactions on VLSI Systems, Vol. 26, No. 6, pp. 1112-1125, June 2018.
51. S. Lee, C. Shi, J. Wang, A. Sanabria, H. Osman, J. Hu and E. Sanchez-Sinencio, “A Built-In Self-Test and In-situ Analog Circuit Optimization Platform,” IEEE Transactions on Circuit and Systems-I, Vol. 65, No. 10, pp. 3445-3458, October 2018.
52. D. Sengupta, F. S. Snigdha, J. Hu and S. Sapatnekar, “An Analytical Approach for Error PMF Characterization in Approximate Circuits,” IEEE Trans. Computer-Aided Design, Vol. 38, No. 1, pp. 70-83, January 2019.
53. F. S. Snigdha, D. Sengupta, J. Hu and S. Sapatnekar, “Dynamic Approximation of JPEG Hardware,” IEEE Trans. Computer-Aided Design, Vol. 38, No. 2, pp. 295-308, February 2019.
54. G. L. Zhang, B. Li, Y. Shi, J. Hu and U. Schlichtmann, “EffiTest2: Efficient Delay Test and Prediction for Post-Silicon Clock Skew Configuration Under Process Variations,” IEEE Trans. Computer-Aided Design, Vol. 38, No. 4, pp. 705-718, April 2019.
55. Y. Yang, J. Hu, D. Porter, T. Marek, K. Heflin, H. Kong and L. Sun, “Deep Reinforcement Learning-Based Irrigation Scheduling,” Transactions of the ASABE, 2020.
56. C. Zhuo, S. Luo, H. Gan, J. Hu and Z. Shi, “Noise Aware DVFS for Efficient Transitions on Battery-Powered IoT Devices,” IEEE Trans. Computer-Aided Design, Vol. 39, No. 7, pp. 1498-1510, July 2020.
57. N. G. Jayasankaran, A. Sanabria Borbon, A. Abuellil, E. Sanchez-Sinencio, J. Hu and J. Rajendran, “Breaking Analog Locking Techniques via Satisfiability Modulo Theories,” IEEE Transactions on VLSI Systems, Vol. 28, No. 10, pp.2157-2170, October 2020.
58. T. Dhar, K. Kunal, Y. Li, M. Madhusudan, J. Poojary, A. K. Sharma, W. Xu, S. M. Burns, R. Harjani, J. Hu, D. A. Kirkpatrick, P. Mukherjee, S. S. Sapatnekar and S. Yaldiz, “ALIGN: A System for Automating Analog Layout,” IEEE Design and Test, Vol. 38, No. 2, pp. 8-18,, 2020.
59. F. S. Snigdha, S. D. Manasi, J. Hu and S. Sapatnekar, “SeFAct2: Selective Feature Activation for Energy-Efficient CNNs using Optimized Thresholds,” IEEE Trans. Computer-Aided Design, Vol. 40, No. 7, pp. 1423-1436, 2020.
60. A. Sanabria-Borbon, N. G. Jayasankaran, J. Hu, J. Rajendran and E. Sanchez-Sinencio, “Analog/RF IP Protection: Attack Models, Defense Techniques, and Challenges,” IEEE Transactions on Circuits and Systems II: Express Briefs, Vol. 68, No. 1., pp. 36-41, 2021.
61. R. Liang, H. Xiang, D. Pandey, L. Reddy, S. Ramji, G.-J. Nam and J. Hu, “Design Rule Violation Prediction at Sub-10nm Process Nodes Using Customized Convolutional Networks”, IEEE Trans. Computer-Aided Design, November 2021.
62. L. Feng, Jeff Huang, J. Hu and A. Reddy, “FastCFI: Real-time Control-Flow Integrity Using FPGA without Code Instrumentation,” ACM Trans. Design Automation of Electronic Systems, Vol. 26, No. 5, pp. 39:1-39:39, May 2021.
63. N. G. Jayasankaran, A. Sanabria Borbon, E. Sanchez-Sinencio, J. Hu and J. Rajendran, “Towards Provably-Secure Analog and Mixed-Signal Locking Against Overproduction,” IEEE Transactions on Emerging Topics in Computing, Vol. 10, No. 1, pp. 386-403,  January-March 2022.
64. L. Feng, Jiayi Huang, Jeff Huang and J. Hu, “Toward Taming the Overhead Monster for Data-flow Integrity,” ACM Trans. Design Automation of Electronic Systems, Vol. 27, No. 3, pp. 25:1-25:24, May 2022.
65. Z. Xie, R. Liang, X. Xu, J. Hu, C.-C. Chang, J. Pan and Y. Chen, “Pre-Placement Net Length and Timing Estimation by Customized Graph Neural Network”, IEEE Trans. Computer-Aided Design, Vol. 41, No. 11, pp. 4667-4680, November 2022.
66. Y. Li, Y. Lin, M. Madhusudan, A. Sharma, S. Sapatnekar, R. Harjani and  J. Hu, “Performance-Driven Wire Sizing for Analog Integrated Circuits,” ACM Trans. Design Automation of Electronic Systems, Vol. 28, No. 2, pp. 19:1-23, December 2022.
67. Z. Xie, J. Pan, C.-C. Chang, J. Hu and Y. Chen, “The Dark Side: Security and Reliability Concerns in Machine Learning for EDA“, IEEE Trans. Computer-Aided Design, Vol. 42, No. 4, pp. 1171-1184, April 2023.
68. K. Kunal, T. Dhar, M. Madhusudan, J. Poojary, A. K. Sharma, W. Xu, S. Burns, J. Hu, R. Harjani, S. S. Sapatnekar, “GNN-Based Hierarchical Annotation for Analog Circuits,” IEEE Trans. Computer-Aided Design, Vol. 42, No. 9, pp. 2801-2814, September 2023.
69. C.-C. Chang, J. Pan, Z. Xie, T. Zhang, J. Hu and Y. Chen, “Towards Fully Automated Machine Learning for Routability Estimator Development”, IEEE Trans. Computer-Aided Design, Vol. 43, No. 3, pp. 970-982, March 2024.
70. Y. Lin, Y. Li, M. Madhusudan, S. S. Sapatnekar, R. Harjani and J. Hu, “MMM: Machine Learning-Based Macro-Modeling for Linear Analog ICs and ADC/DACs,” IEEE Trans. Computer-Aided Design, Vol. 43, No. 12, pp. 4740-4752, December 2024.
71. J. Song, R. Liang, B. Yuan and J. Hu, “DiMO-CNN: Deep Learning Toolkit-Accelerated Analytical Modeling and Optimization of CNN Hardware and Dataflow,” IEEE Trans. Computer-Aided Design, Vol. 44, No. 1, pp. 251-265, January 2025.
72. D. Fang, B. Zhang, H. Hu, W. Li, B. Yuan and J. Hu, “Global Placement Exploiting Soft 2D Regularity”, ACM Trans. Design Automation of Electronic Systems, Vol. 30, No. 2, pp. 17:1-21, January 2025.
73. J. Pan, G. Zhou, C.-C. Chang, I. Jacobson, J. Hu and Y. Chen, “A Survey of Research in Large Language Models for Electronic Design Automation”, ACM Trans. Design Automation of Electronic Systems, Vol. 30, No. 3, pp. 34:1-21, February 2025.
74. D. Puckett, T. Tomer, P.V. Gratz, J. Hu, G. Shipman, J. Dominguez-Trujillo, K. Sheridan, “Estimating CPI Stacks from Multiplexed Performance Counter Data using Machine Learning”, IEEE Computer Architecture Letters, 2025.

1. J. Hu and S. S. Sapatnekar, “Simultaneous buffer insertion and non-Hanan optimization for VLSI interconnect under a higher order AWE model,” Proc. ACM International Symposium on Physical Design, pp. 133-138, 1999.
2. J. Hu and S. S. Sapatnekar, “FAR-DS: Full-plane AWE Routing with Driver Sizing”, Proc. ACM/IEEE Design Automation Conference, pp. 84-89, 1999.
3. J. Hu and S. S. Sapatnekar, “A timing-constrained algorithm for simultaneous global routing of multiple nets,” Proc. IEEE/ACM International Conference on Computer-Aided Design, pp. 99-103, 2000.
4. C. J. Alpert, G. Gandham, M. Hrkic, J. Hu, A. B. Kahng, J. Lillis, B. Liu, S. T. Quay, S. S. Sapatnekar, A. J. Sullivan and P. G. Villarrubia, “Buffered Steiner trees for difficult instances,”Proc. ACM International Symposium on Physical Design, pp. 4-9, 2001.
5. C. J. Alpert, G. Gandham, J. Hu, J. L. Neves, S. T. Quay and S. S. Sapatnekar, “Steiner tree optimization for buffers, blockages and bays,” Proc. IEEE International Symposium on Circuits and Systems, pp. 399-402, 2001.
6. C. J. Alpert, J. Hu, S. S. Sapatnekar and P. G. Villarrubia, “A practical methodology for early buffer and wire resource allocation,” Proc. ACM/IEEE Design Automation Conference, pp. 189-194, 2001. (Best Paper Award)
7. J. Hu and S. S. Sapatnekar, “Performance driven global routing through gradual refinement,” Proc. IEEE International Conference on Computer Design, pp. 481-483, 2001.
8. J. Hu, C. J. Alpert, S. T. Quay and G. Gandham, “Buffer insertion with adaptive blockage avoidance,” Proc. ACM International Symposium on Physical Design, pp. 92-97, 2002.
9. C. J. Alpert, C. Chu, G. Gandham, M. Hrkic, J. Hu, C. Kashyap and S. T. Quay, “Simultaneous driver sizing and buffer insertion using a delay penalty estimation technique,” Proc. ACM International Symposium on Physical Design, pp. 104-109, 2002.
10. H. Su, J. Hu, S. S. Sapatnekar and S. Nassif, “Congestion-driven codesign of power and signal networks,” Proc. ACM/IEEE Design Automation Conference, pp. 64-69, 2002.
11. C. J. Alpert, G. Gandham, M. Hrkic, J. Hu and S. T. Quay, “Porosity aware buffered Steiner tree construction,” Proc. ACM International Symposium on Physical Design, pp. 158-165, 2003.
12. B. Lu, J. Hu, G. Ellis and H. Su, “Process variation aware clock tree routing,” Proc. ACM International Symposium on Physical Design, pp. 174-181, 2003.
13. R. Chaturvedi and J. Hu, “A simple yet effective merging scheme for prescribed-skew clock routing,” Proc. IEEE International Conference on Computer Design, pp. 282-287, 2003.
14. A. Rajaram, B. Lu, W. Guo, R. Mahapatra and J. Hu, “Analytical bound for unwanted clock skew due to wire width variation,” Proc. IEEE/ACM International Conference on Computer-Aided Design, pp. 401-406, 2003.
15. C. N. Sze, J. Hu and C. J. Alpert, “Place and route aware buffered Steiner tree construction,” Proc. Asia and South Pacific Design Automation Conference, pp. 355- 360, 2004. (Best Paper Nominee)
16. D. Wu, J. Hu, R. Mahapatra and M. Zhao, “Layer assignment for crosstalk risk minimization,” Proc. Asia and South Pacific Design Automation Conference, pp. 159-162, 2004.
17. K. Cao, J. Hu and M. Cheng, “Layout modification for library cell Alt-PSM composability,” Proc. SPIE, Vol. 5379, pp. 253-259, 2004.
18. R. Chaturvedi and J. Hu, “Buffered clock tree for high quality IC designs,” Proc. IEEE International Symposium on Quality Electronic Design, pp. 381-386, 2004.
19. A. Rajaram, J. Hu and R. Mahapatra, “Reducing clock skew variability via cross links,” Proc. ACM/IEEE Design Automation Conference, pp. 18-23, 2004. (Best Paper Nominee)
20. C. J. Alpert, M. Hrkic, J. Hu and S. T. Quay, “Fast and flexible buffer trees that navigate the physical layout environment,” Proc. ACM/IEEE Design Automation Conference, pp. 24-29, 2004.
21. C. J. Alpert, J. Hu, S. S. Sapatnekar and C.-N. Sze, “Accurate estimation of global buffer delay within a floorplan,” Proc. IEEE/ACM International Conference on Computer-Aided Design, pp. 706-711, 2004.
22. V. Seth, M. Zhao and J. Hu, “Exploiting level sensitive latches in wire pipelining,” Proc. IEEE/ACM International Conference on Computer-Aided Design, pp. 283-290, 2004.
23. Z. Li, C.-N. Sze, C. J. Alpert, J. Hu and W. Shi, “Making fast buffer insertion even faster via approximation techniques,” Proc. Asia and South Pacific Design Automation Conference, pp. 13-18, 2005.
24. K. Cao, P. Dhawan and J. Hu, “Library cell layout with Alt-PSM compliance and composability,” Proc. Asia and South Pacific Design Automation Conference, pp. 216-219, 2005.
25. D. Wu, J. Hu, M. Zhao and R. Mahapatra, “Timing driven track routing considering coupling capacitance,” Proc. Asia and South Pacific Design Automation Conference, pp. 1156-1159, 2005.
26. G. Venkataraman, C.-N. Sze and J. Hu, “Skew scheduling and clock routing for improved tolerance to process variations,” Proc. Asia and South Pacific Design Automation Conference, pp. 594-599, 2005.
27. L. Huang, Y. Cai, Q. Zhou, X. Hong, J. Hu and Y. Lu, “Clock network minimization methodology based on incremental placement,” Proc. Asia and South Pacific Design Automation Conference, pp. 99-102, 2005.
28. Y. Lu, C.-N. Sze, X. Hong, Q. Zhou, Y. Cai, L. Huang and J. Hu, “Register placement for low power clock network,” Proc. Asia and South Pacific Design Automation Conference, pp. 588-593, 2005.
29. D. Wu, J. Hu and R. Mahapatra, “Coupling aware timing optimization and antenna avoidance in layer assignment,” Proc. ACM International Symposium on Physical Design, pp. 20-27, 2005.
30. A. Rajaram, D. Pan and J. Hu, “Improved algorithms for link based non-tree clock network for skew variability reduction,” Proc. ACM International Symposium on Physical Design, pp. 55-62, 2005.
31. Y. Lu, C.-N. Sze, X. Hong, Q. Zhou, Y. Cai, L. Huang and J. Hu, “Navigating registers in placement for clock network minimization,” Proc. ACM/IEEE Design Automation Conference, pp. 176-181, 2005.
32. C.-N. Sze, C. J. Alpert, J. Hu and W. Shi, “Path based buffer insertion,” Proc. ACM/IEEE Design Automation Conference, pp. 509-514, 2005.
33. D. Wu, G. Venkataraman, J. Hu, Q. Li and R. Mahapatra, “DiCER: Distributed and Cost-Effective Redundancy for variation tolerance,” Proc. IEEE/ACM International Conference on Computer-Aided Design, pp. 393-397, 2005.
34. G. Venkataraman, N. Jayakumar, J. Hu, P. Li, S. Khatri, A. Rajaram, P. McGuinness and C. J. Alpert, “Practical techniques to reduce skew and its variations in buffered clock networks,”Proc. IEEE/ACM International Conference on Computer-Aided Design, pp. 592-596, 2005.
35. G. Venkataraman, J. Hu, F. Liu and C. N. Sze, “Integrated placement and skew optimization for rotary clocking,” Proc. ACM/IEEE Design Automation and Test in Europe, pp. 756-761, 2006.
36. M.-S. Kim and J. Hu, “Associative skew clock routing for difficult instances,” Proc. ACM/IEEE Design Automation and Test in Europe, pp. 762-767, 2006.
37. C. Zhuo, J. Hu and K. Chen, “An improved AMG-based method for fast power grid analysis,” Proc. IEEE International Symposium on Quality Electronic Design, pp. 290-295, 2006.
38. Z. Feng, P. Li and J. Hu, “Efficient model update for general link-insertion networks,” Proc. IEEE International Symposium on Quality Electronic Design, pp. 43-50, 2006.
39. U. Padmanabhan, J. M. Wang and J. Hu, “Statistical clock tree routing for robustness to process variations,” Proc. ACM International Symposium on Physical Design, pp. 149-156, 2006.
40. B.-Y. Su, Y.-W. Chang and J. Hu, “An optimal jumper insertion algorithm for antenna effect avoidance/fixing on general routing trees with obstacles,” Proc. ACM International Symposium on Physical Design, pp. 56-63, 2006.
41. W. Shen, Y. Cai, J. Hu, X. Hong and B. Lu, “High performance clock routing in X-architecture,” Proc. IEEE International Symposium on Circuits and Systems, pp. 2081-2084, 2006.
42. S. Hu, Q. Li, J. Hu and P. Li, “Steiner network construction for timing critical nets,” Proc. ACM/IEEE Design Automation Conference, pp. 379-384, 2006.
43. S. Hu, C. J. Alpert, J. Hu, S. Karandikar, Z. Li, W. Shi and C. N. Sze, “Fast algorithms for slew constrained minimum cost buffering,” Proc. ACM/IEEE Design Automation Conference, pp. 308-313, 2006.
44. K. Cao, S. Dobre and J. Hu, “Standard cell characterization considering lithography induced variations,” Proc. ACM/IEEE Design Automation Conference, pp. 801-804, 2006.
45. R. Samanta, G. Venkataraman and J. Hu, “Clock buffer polarity assignment for power noise reduction,” IEEE/ACM International Conference on Computer-Aided Design, pp.558-562, 2006.
46. G. Venkataraman, Z. Feng, J. Hu and P. Li, “Combinatorial algorithms for fast clock mesh optimization,” IEEE/ACM International Conference on Computer-Aided Design, pp. 563-567, 2006.
47. Z. Jiang, S. Hu, J. Hu, Z. Li and W. Shi, “A new RLC buffer insertion algorithm,” IEEE/ACM International Conference on Computer-Aided Design, pp. 553-557, 2006.
48. C. Zhuo, J. Hu, M. Zhao and K. Chen, “Fast decap allocation method based on algebraic multigrid,” IEEE/ACM International Conference on Computer-Aided Design, pp. 107-111, 2006.
49. G. Venkataraman, J. Hu, “A placement methodology for robust clocking,” International Conference on VLSI Design, pp. 881-886, 2007.
50. B. Liu, A. B. Kahng, X. Xu, J. Hu and G. Venkataraman, “A global minimum clock distribution network augmentation algorithm for guaranteed clock skew yield,” Asia and South Pacific Design Automation Conference, pp. 24-31, 2007.
51. K. Cao, J. Hu and M. Cheng, “Wire sizing and spacing for lithographic printability optimization,” SPIE Advanced Lithography, pp. 652111:1-9, 2007.
52. S. Hu and J. Hu, “Pattern sensitive placement for manufacturability,” ACM International Symposium on Physical Design, pp. 27-34, 2007.
53. Z. Jiang, S. Hu, J. Hu and W. Shi, “An efficient algorithm for RLC buffer insertion,” IEEE International Symposium on Quality Electronic Design, pp. 171-175, 2007.
54. W. Shen, Y. Cai, X. Hong, J. Hu and B. Lu, “Planar-CRX: a single-layer zero skew clock routing in X-architecture,” IEEE International Symposium on Quality Electronic Design, pp. 299-304, 2007.
55. Y. Liu, T. Zhang and J. Hu, “Soft clock skew scheduling for system-level variation tolerance in digital signal processing circuits,” IEEE International Symposium on Quality Electronic Design, pp. 749-754, 2007.
56. W. Shen, Y. Cai, X. Hong and J. Hu, “Activity-aware register placement for low power gated clock tree construction,” IEEE Computer Society Annual Symposium on VLSI, pp. 383-388, 2007.
57. S. Hu, M. Ketkar and J. Hu, “Gate sizing for cell library based designs,” ACM/IEEE Design Automation Conference, pp. 847-852, 2007.
58. S. Hu and J. Hu, “Unified adaptivity optimization of clock and logic signals,” IEEE/ACM International Conference on Computer-Aided Design, pp. 125-130, 2007.
59. C. Zhuo, H. Zhang, R. Samanta, J. Hu and K. Chen, “Modeling, optimization and control of rotary traveling-wave oscillator,” IEEE/ACM International Conference on Computer-Aided Design, pp. 476-480, 2007.
60. X. Ye, P. Li, M. Zhao, R. Panda and J. Hu, “Analysis of large clock meshes via harmonic-weighted model order reduction and port sliding,” IEEE/ACM International Conference on Computer-Aided Design, pp. 627-631, 2007.
61. S. Hu and J. Hu, “A new fast slew buffering algorithm without input slew assumptions,” IEEE Dallas Circuits and Systems Workshop on System-on-Chip, pp. 1-4, 2007.
62. Y. Wang, Q. Zhou, Y. Cai, J. Hu and X. Hong, “Low power clock buffer planning methodology in FD placement for large scale circuit design,” Asia and South Pacific Design Automation Conference, pp. 370-375, 2008.
63. S. Varadan, J. M. Wang and J. Hu, “Handling partial correlations in yield prediction,” Asia and South Pacific Design Automation Conference, pp. 543-548, 2008.
64. R. Samanta, G. Venkataraman, N. Shah and J. Hu, “Elastic timing scheme for energy-efficient and robust performance,” IEEE International Symposium on Quality Electronic Design, pp. 537-542, 2008.
65. X. Ye, M. Zhao, R. Panda, P. Li and J. Hu, “Accelerating clock mesh simulation using matrix-level macromodels and dynamic time step rounding,” IEEE International Symposium on Quality Electronic Design, pp. 627-632, 2008.
66. Y. Liu, J. Hu and W. Shi, “Multi-scenario buffer insertion in multi-core processor designs,” ACM International Symposium on Physical Design, pp. 15-22, 2008.
67. R. Samanta, J. Hu and P. Li, “Discrete buffer and wire sizing for link-based non-tree clock networks,” ACM International Symposium on Physical Design, pp. 175-181, 2008.
68. W. Shen, Y. Cai, X. Hong and J. Hu, “Activity and register placement aware gated clock network design,” ACM International Symposium on Physical Design, pp. 182-189, 2008.
69. N. Shah, R. Samanta, M. Zhang, J. Hu and D. Walker, “Built-in proactive tuning system for circuit aging resilience,” IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, pp. 96-104, 2008.
70. W. Shen, Y. Cai, X. Hong and J. Hu, “Gate planning during placement for gated clock network,” IEEE International Conference on Computer Design, pp. 128-133, 2008.
71. Y. Liu, R. Shelar and J. Hu, “Delay-optimal simultaneous technology mapping and placement with applications to timing optimization,” IEEE/ACM International Conference on Computer-Aided Design, pp. 101-106, 2008.
72. Y. Liu and J. Hu, “A new algorithm for simultaneous gate sizing and threshold voltage assignment,” ACM International Symposium on Physical Design, pp. 27-34, 2009. (Best Paper Nominee)
73. P. Shah and J. Hu, “Impact of lithography-friendly circuit layout,” ACM/IEEE Great Lakes Symposium on VLSI, pp. 385-388, 2009.
74. M. A. R. Chaudhry, Z. Asad, A. Sprintson and J. Hu, “Efficient rerouting algorithms for congestion mitigation,” IEEE Computer Society Annual Symposium on VLSI, pp. 43-48, 2009.
75. N. Nemade, A. Sprintson and J. Hu, “Applications of network coding in global routing,” IEEE International Conference on IC Design and Technology, pp. 55-58, 2009.
76. Y. Liu and J. Hu, “GPU-based parallelization for fast circuit optimization,” ACM/IEEE Design Automation Conference, pp. 943-946, 2009.
77. S. Prabhu, B. Grot, P. V. Gratz and J. Hu, “Ocin-tsim: DVFS aware simulator for NoCs,” Workshop on SoC Architecture, Accelerators and Workloads, 2010.
78. Y. Wei, J. Hu, F. Liu and S. Sapatnekar, “Physical design techniques for optimizing RTA-induced variations,” Asia and South Pacific Design Automation Conference, pp. 745-750, 2010.
79. F. Yang, Y. Cai, Q. Zhou and J. Hu, “SAT based multi-net rip-up-and-reroute for manufacturing hotspot removal,” Design Automation and Test in Europe, pp. 1369-1372, 2010.
80. K.-N. Shim, J. Hu and J. Silva-Martinez, “A dual-level adaptive supply voltage system for variation resilience,” IEEE International Symposium on Quality Electronic Design, pp. 38-43, 2010.
81. V. R. Mekala, Y. Liu, X. Ye, P. Li and J. Hu, “Accurate clock mesh sizing via sequential quadratic programming,” ACM International Symposium on Physical Design, pp. 135-142, 2010.
82. T. Jindal, C. J. Alpert, J. Hu, Z. Li, G.-J. Nam and C. B. Winn, “Detecting tangled logic structures in VLSI netlists,” ACM/IEEE Design Automation Conference, pp. 603-608, 2010.
83. Y. Liu, Y. Yang and J. Hu, “Clustering-based simultaneous task and voltage scheduling for NOC systems,” IEEE/ACM International Conference on Computer-Aided Design, pp. 277-283, 2010.
84. K.-N. Shim and J. Hu, “Transient and fine-grained voltage adaptation for variation resilience in VLSI interconnects,” IEEE International Symposium on Quality Electronic Design, pp. 80-86, 2011.
85. Y.-L. Huang, J. Hu and W. Shi, “Lagrangian relaxation for gate implementation selection,” ACM International Symposium on Physical Design, pp. 167-174, 2011.
86. X. Chen, J. Hu and N. Xu, “Regularity-constrained floorplanning for multi-core processors,” ACM International Symposium on Physical Design, pp. 99-105, 2011.
87. M. Ozdal, S. Burns and J. Hu, “Gate sizing and device technology selection algorithms for high-performance industrial designs,” IEEE/ACM International Conference on Computer-Aided Design, pp. 724-731, 2011. (Best Paper Award)
88. X. Chen, Z. Xu, H. Kim, P. Gratz, J. Hu, M. Kishinevsky and U. Ogras, “In-network monitoring and control policy for DVFS of CMP networks-on-chip and last level caches,” IEEE/ACM International Symposium on Networks-on-Chip, pp. 43-50, 2012. (Best Paper Nominee)
89. Q. Zhao and J. Hu, “Track assignment considering crosstalk-induced performance degradation,” IEEE International Conference on Computer Design, pp. 506-507, 2012.
90. K.-N. Shim and J. Hu, “A low overhead built-in delay testing with voltage and frequency adaptation for variation resilience,” IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, pp. 170-177, 2012.
91. X. Chen, Z. Xu, H. Kim, P. Gratz, J. Hu, M. Kishinevsky, U. Ogras and R. Ayoub, “Dynamic voltage and frequency scaling for shared resources in multicore processor designs,” ACM/IEEE Design Automation Conference, 2013.
92. D. Kadjo, H. Kim, P. Gratz, J. Hu and R. Ayoub, “Power gating with block migration in chip-multiprocessor last-level caches,” IEEE International Conference on Computer Design, pp. 93-99, 2013.
93. G. Yang, H. He and J. Hu, “Resource allocation algorithms for guaranteed service in application-specific NoCs,” IEEE International Conference on Computer Design, pp. 483-486, 2013.
94. J.-Y. Won, X. Chen, P. Gratz, J. Hu and V. Soteriou, “Up by their bootstraps: online learning in artificial neural networks for CMP uncore power management,” IEEE International Symposium on High Performance Computer Architecture, pp. 308-319, 2014. (HiPEAC Paper Award)
95. A. Singh and J. Hu, “Low power and variation tolerant design using planar asymmetric double gate transistor,” IEEE International Midwest Symposium on Circuits and Systems, pp. 1021-1024, 2014.
96. H. He, G. Yang and J. Hu, “Algorithms for power-efficient QoS in application specific NoCs,” ACM/IEEE International Symposium on Low Power Electronics and Design, pp. 165-170, 2014.
97. S. Rasheed, P. Gratz, S. Shakkottai and J. Hu, “STORM: a Simple Traffic-Optimized Router Microarchitecture for networks-on-chip,” IEEE/ACM International Symposium on Networks-on-Chip, pp. 176-177, 2014.
98. R. Kumar, B. Li, Y. Shen, U. Schlichtmann and J. Hu, “Timing Verification for Adaptive Integrated Circuits,” ACM/IEEE Design Automation and Test in Europe, pp. 1587-1590, 2015.
99. C. Li, W. Luo, S. Sapatnekar and J. Hu, “Joint Precision Optimization and High Level Synthesis for Approximate Computing,” ACM/IEEE Design Automation Conference, 2015.
100. J. Wang, C. Shi, E. Sanchez-Sinencio and J. Hu, “Built-In Self Optimization for Variation Resilience of Analog Filters,” IEEE Computer Society Annual Symposium on VLSI, pp. 656-661, 2015.
101. H. He, J. Wang and J. Hu, “Collaborative Gate Implementation Selection and Adaptivity Assignment for Robust Combinational Circuits,” ACM/IEEE International Symposium on Low Power Electronics and Design, pp. 122-127, 2015.
102. J.-Y. Won, P.V. Gratz, S. Shakkottai and J. Hu, “Having Your Cake and Eating It Too: Energy Savings without Performance Loss Through Resource Sharing Driven Power Management,”ACM/IEEE International Symposium on Low Power Electronics and Design, pp. 255-260, 2015.
103. C.-Y. Wu, H. Graeb and J. Hu, “A Pre-search Assisted ILP Approach to Analog Integrated Circuit Routing,” IEEE International Conference on Computer Design, pp. 244-250, 2015.
104. Y. Shen and J. Hu, “GPU Acceleration for PCA-Based Statistical Static Timing Analysis,” IEEE International Conference on Computer Design, pp. 674-679, 2015.
105. H. Zhou, J. Hu, S. Khatri, F. Liu, C. C.-N. Sze and M. R. Yousefi, “GPU Acceleration for Bayesian Control of Markovian Genetic Regulatory Networks,” IEEE International Conference on Biomedical and Health Informatics, 2016.
106. A. Lu, H. He and J. Hu, “Proximity Optimization for Adaptive Circuit Design,” ACM International Symposium on Physical Design, 2016.
107. Y. Wang, P. Chen, J. Hu and J. Rajendran, “The Cat and Mouse in Split Manufacturing,” ACM/IEEE Design Automation Conference, 2016.
108. F. S. Snigdha, D. Sengupta, J. Hu and S. S. Sapatnekar, “Optimal Design of JPEG Hardware under the Approximate Computing Paradigm,” ACM/IEEE Design Automation Conference, 2016.
109. C. Li, S. S. Sapatnekar and J. Hu, “Control Synthesis and Delay Sensor Deployment for Efficient ASV Designs,” IEEE/ACM International Conference on Computer-Aided Design, 2016.
110. Y. Wang, P. Chen, J. Hu and J. Rajendran, “Routing Perturbation for Enhanced Security in Split Manufacturing,” Asia and South Pacific Design Automation Conference, 2017.
111. H. He, J. Hu and D. Da Silva, “Enhancing Datacenter Resource Management through Temporal Logic Constraints,” IEEE International Parallel and Distributed Processing Symposium, 2017.
112. D. Sengupta, F. S. Snigdha, J. Hu and S. S. Sapatnekar, “SABER: Selection of Approximate Bits for the Design of Error Tolerant Circuits,” ACM/IEEE Design Automation Conference, 2017.
113. W. Xu, S. S. Sapatnekar and J. Hu, “A Simple Yet Efficient Accuracy Configurable Adder Design,” ACM/IEEE International Symposium on Low Power Electronics and Design, 2017.
114. L. Sun, Y. Liu, L. Liu, J. Hu and S. Hu, “A Comparative Study on Neural Network-Based Prediction of Smart Community Energy Consumption,” IEEE Smart World Congress, 2017.
115. H. Zhou, S. Khatri, J. Hu, F. Liu and C. Sze, “Fast and Highly Scalable Bayesian MDP on a GPU Platform,” ACM Conference on Bioinformatics, Computational Biology, and Health Informatics, 2017.
116. C. Li, D. Sengupta, F. S. Snigdha, W. Xu, J. Hu, and S. S. Sapatnekar, “Special Session: A Quantifiable Approach to Approximate Computing,” IEEE/ACM International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, 2017.
117. J. Wang, C. Shi, A. Sanabria-Borbon, E. Sanchez-Sinencio and J. Hu, “Thwarting Analog IC Piracy via Combinational Locking,” IEEE International Test Conference, 2017.
118. L. Feng, Y. Wang, W.-K. Mak, J. Rajendran and J. Hu, “Making Split Fabrication Synergistically Secure and Manufacturable,” IEEE/ACM International Conference on Computer-Aided Design, 2017.
119. Y. Wang, T. Cao, J. Hu and J. Rajendran, “Front-End-of-Line Attacks in Split Manufacturing,” IEEE/ACM International Conference on Computer-Aided Design, 2017.
120. L. Sun, Y. Yang, J. Hu, D. Porter, T. Marek and C. Hillyer, “Reinforcement Learning Control for Water-Efficient Agricultural Irrigation,” IEEE International Conference on Ubiquitous Computing and Communications, 2017.
121. Y. Yang, L. Sun, J. Hu, D. Porter, T. Marek and C. Hillyer, “A Reliable Soil Moisture Sensing Methodology for Agricultural Irrigation,” IEEE International Conference on Ubiquitous Computing and Communications, 2017.
122. J. Hu, Y. Zhou, Y. Wei, S. Quay, L. Reddy, G. Tellez, G.-J. Nam, “Interconnect Optimization Considering Multiple Critical Paths,” ACM International Symposium on Physical Design, 2018.
123. L. Huang, Y. Li, S. Sapatnekar and J. Hu, “Using Imprecise Computing for Improved Non-preemptive Real-time Scheduling,” ACM/IEEE Design Automation Conference, 2018.
124. L. Feng, P. Kudva, D. Da Silva and J. Hu, “Exploring Serverless Computing for Neural Network Training,” IEEE International Conference on Cloud Computing, 2018.
125. D. Porter, T. Marek, L. Sun, Y. Yang, J. Hu and K. Heflin, “Integration of Data and Advanced Technologies to Improve Center Pivot Irrigation Management,” ASABE Annual International Meeting, 2018.
126. H. Kong, J. Cheng, K. Narayanan and J. Hu, “DUCER: a Fast and Lightweight Error Correction Scheme for In-Vehicle Network,” IEEE International Conference on Vehicular Electronics and Safety, 2018. (Best Paper Award)
127. L. Huang, I.-H. Hou, S. S. Sapatnekar and J. Hu, “Graceful Degradation of Low-Criticality Tasks in Multiprocessor Dual-Criticality Systems,” International Conference on Real-Time Networks and Systems, 2018.
128. Z. Xie, Y.-H. Huang, G.-Q. Fang, H. Ren, S.-Y. Fang, Y. Chen and J. Hu, “RouteNet: Routability Prediction for Mixed-Size Designs Using Convolutional Neural Network,” IEEE/ACM International Conference on Computer-Aided Design, 2018.
129. N. G. Jayasankaran, A. S. Borbon, E. Sanchez-Sinencio, J. Hu and J. Rajendran, “Towards Provably-Secure Analog and Mixed-Signal Locking Against Overproduction,” IEEE/ACM International Conference on Computer-Aided Design, 2018.
130. W. Xu, L. Feng, J. Rajendran and J. Hu, “Layout Recognition Attacks on Split Manufacturing,” ACM/IEEE Asia and South-Pacific Design Automation Conference, 2019.
131. F. S. Snigdha, I. Ahmed, S. D. Manasi, M. G. Mankalale, J. Hu and S. S. Sapatnekar, “SeFAct: Selective Feature Activation and Early Classification for CNNs,” ACM/IEEE Asia and South-Pacific Design Automation Conference, 2019.
132. Y.-H. Huang, Z. Xie, G.-Q. Fang, T.-C. Yu, H. Ren, S.-Y. Fang, Y. Chen and J. Hu, “Routability-Driven  Macro Placement with Embedded CNN-Based Prediction Model,” ACM/IEEE Design Automation and Test, Europe, 2019.
133. C. Li, S. Saptnekar and J. Hu, “Fast Mapping-Based High-Level Synthesis of Pipelined Circuits,” IEEE International Symposium on Quality Electronic Design, 2019.
134. H. Zhou, S. Khatri, J. Hu and F. Liu, “A Memory-Efficient Markov Decision Process Computation Framework Using BDD-based Sampling Representation,” ACM/IEEE Design Automation Conference, 2019.
135. E. C. Barboza, N. Shukla, Y. Chen and J. Hu, “Machine Learning-Based Pre-Routing Timing Prediction with Reduced Pessimism,” ACM/IEEE Design Automation Conference, 2019.
136. K. Kunal, M. Madhusudan, A. K. Sharma, W. Xu, S. M. Burns, R. Harjani, J. Hu, D. A. Kirkpatrick and S. S. Sapatnekar, “ALIGN: Open-Source Analog Layout Automation from the Group Up,” ACM/IEEE Design Automation Conference, 2019.
137. Y. Yang, J. Hu, D. Porter, T. Marek, K. Heflin, H. Kong and L. Sun, “Deep Reinforcement Learning Irrigation Planning and Automated Scheduling for Fixed Zone Irrigation Systems,” ASABE Annual International Meeting, 2019.
138. L. Huang, I.-H. Hou, S. S. Sapatnekar and J. Hu, “Improving QoS for Global Dual-Criticality Scheduling on Multiprocessors,” IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, 2019.
139. L. Feng, J. Huang, J. Hu and A. Reddy, “FastCFI: Real-Time Control Flow Integrity using FPGA without Code Instrumentation,” International Conference on Runtime Verification, 2019.
140. N. G. Jayasankaran, A. S. Borbon, A. Abuellil, E. Sánchez-Sinencio, J. Hu and J. Rajendran, “Breaking Analog Locking Techniques via Satisfiability Modulo Theories,” IEEE International Test Conference, 2019.
141. Z. Xie, G.-Q. Fang, Y.-H. Huang, H. Ren, Y. Zhang, B. Khailany, S.-Y. Fang, J. Hu, Y. Chen and E. C. Barboza, “FIST: A Feature-Importance Sampling and Tree-Based Method for Automatic Design Flow Parameter Tuning,” ACM/IEEE Asia and South-Pacific Design Automation Conference, 2020.
142. Z. Xie, H. Ren, B. Khailany, Y. Sheng, S. Santosh, J. Hu and Y. Chen, “PowerNet: Transferable Dynamic IR Drop Estimation via Maximum Convolutional Neural Network,” ACM/IEEE Asia and South-Pacific Design Automation Conference, 2020.
143. H. Zhou, S. P. Khatri, J. Hu and F. Liu, “Scaled Population Arithmetic for Efficient Stochastic Computing,” ACM/IEEE Asia and South-Pacific Design Automation Conference, 2020.
144. C. Yang, H. Li, Y. Chen and J. Hu, “Enhancing Generalization of Wafer Defect Detection by Data Discrepancy-aware Preprocessing and Contrast-varied Augmentation,” ACM/IEEE Asia and South-Pacific Design Automation Conference, 2020.
145. K. Kunal, T. Dhar, M. Madhusudan, J. Poojary, A. K. Sharma, W. Xu, S. Burns, J. Hu, R. Harjani and S. S. Sapatnekar, “GANA: Graph Convolutional Network Based Automated Netlist Annotation for Analog Circuits,” ACM/IEEE Design Automation and Test in Europe, 2020.
146. S. Gogri, J. Hu, A. Tyagi, M. Quinn, S. Ramachandran, F. Batool and A. Shikaripura, “Machine Learning-Guided Stimulus Generation for Functional Verification,” Design and Verification Conference and Exhibition, 2020.
147. R. Liang, H. Xiang, D. Pandey, L. Reddy, S. Ramji, G.-J. Nam and J. Hu, “DRC Hotspot Prediction at Sub-10nm Process Nodes Using Customized Convolutional Network,” ACM International Symposium on Physical Design, 2020.
148. K. Kunal, T. Dhar, Y. Li, M Madhusudan, J. Poojary, A. K. Sharma, W. Xu, S. M. Burns, R. Harjani, J. Hu, P. Mukherjee and S. S. Sapatnekar, “Learning from Experience: Applying ML to Analog Circuit Design,” ACM International Symposium on Physical Design, 2020.
149. Y. Li, Y. Lin, M. Madhusudan, A. Sharma, W. Xu, S. Sapatnekar, R. Harjani and J. Hu, “Exploring a Machine Learning Approach to Performance Driven Analog IC Placement,” IEEE Computer Society Annual Symposium on VLSI, 2020.
150. Y. Li, Y. Lin, M. Madhusudan, A. Sharma, W. Xu, S. Sapatnekar, R. Harjani and J. Hu, “A Customized Graph Neural Network Model for Guiding Analog IC Placement,” IEEE/ACM International Conference on Computer-Aided Design, 2020.
151. R. Liang, Z. Xie, J. Jung, V. Chauhan, Y. Chen, J. Hu, H. Xiang and G.-J. Nam, “Routing-Free Crosstalk Prediction,” IEEE/ACM International Conference on Computer-Aided Design, 2020.
152. Z. Xie, H. Li, X. Xu, J. Hu and Y. Chen, “Fast IR Drop Estimation with Machine Learning,” IEEE/ACM International Conference on Computer-Aided Design, 2020.
153. A. C. Sanabria-Borbon, N. G. Jayasankaran, S. Lee, J. Hu, J. Rajendran and E. Sanchez-Sinencio, “Schmitt Trigger-Based Key Provisioning for Locking Analog/RF Integrated Circuits,” IEEE International Test Conference, 2020.
154. K. Bharathi, J. Hu and S. P. Khatri, “Scaled Population Subtraction for Stochastic Computation,” IEEE International Conference on Computer Design, 2020.
155. H. Kong, L. Feng, C. Deng, B. Yuan and J. Hu, “How Much Does Regularity Help FPGA Placement?,” International Conference on Field Programmable Technology, 2020.
156. Z. Xie, R. Liang, X. Xu, J. Hu, Y. Duan and Y. Chen, “Net2: A Graph Neural Network Method Customized for Pre-Layout Wirelength Estimation,” ACM/IEEE Asia and South-Pacific Design Automation Conference, 2021.
157. T. Dha, J. Poojary, Y. Li, K. Kunal, M. Madhusudan, A. K. Sharma, S. D. Manasi, J. Hu, R. Harjani and S. Sapatnekar, “Fast and Efficient Constraint Evaluation of Analog Layout using Machine Learning Models,” ACM/IEEE Asia and South-Pacific Design Automation Conference, 2021.
158. M. Madhusudan, A. K. Sharma, Y. Li, J. Hu, S. S. Sapatnekar, R. Harjani “Analog Layout Generation using Optimized Primitives,” Proc. ACM/IEEE Design Automation and Test in Europe, 2021.
159. T. Dhar, K. Kunal, Y. Li, Y. Lin, M. Madhusudan, J. Poojary, A. K. Sharma, S. Burns, R. Harjani, J. Hu, P. Mukherjee, S. Yaldiz and S. S. Sapatnekar, “Machine Learning Techniques in Analog Layout Automation,” ACM International Symposium on Physical Design, 2021.
160. E. C. Barboza, S. Jacob, M. Ketkar, M. Kishinevsky, P. Gratz and J. Hu, “Automatic Microprocessor Performance Bug Detection,” IEEE International Symposium on High Performance Computer Architecture, 2021.
161. Y. Li, Y. Lin, M. Madhusudan, A. Sharma, S. Sapatnekar, R. Harjani and J. Hu, “A Circuit Attention Network-Based Actor-Critic Learning Approach to Robust Analog Transistor Sizing,” ACM/IEEE Workshop on Machine Learning for CAD, 2021.
162. Z. Xie, X. Xu, M. Walker, J. Knebel, K. Palaniswamy, N. Hebert, J. Hu, H. Yang, Y. Chen and S. Das, “APOLLO: An Automated Power Modeling Framework for Runtime Power Introspection in High-Volume Commercial Microprocessors,” IEEE/ACM International Symposium on Microarchitecture (Best Paper Award), 2021.
163. R. Liang, J. Jung, , H. Xiang, L. Reddy, A. Lvov, J. Hu and G.-J. Nam, “FlowTuner: A Multi-Stage EDA Flow Tuner Exploiting Parameter Knowledge Transfer,” IEEE/ACM International Conference on Computer-Aided Design, 2021.
164. J. Liu, S. Su, M. Madhusudan, M. Hassanpourghadi, S. Saunders, Q. Zhang, R. Rasul, Y. Li, J. Hu, A. Sharma, S. Sapatnekar, R. Harjani, A. Levi, S. Gupta and M. Chen, “From Specification to Silicon: Towards Analog/Mixed-Signal Design Automation using Surrogate NN Models with Transfer Learning,” IEEE/ACM International Conference on Computer-Aided Design, 2021.
165. C.-C. Chang, J. Pan, T. Zhang, Z. Xie, J. Hu, W. Qi, C.-W. Lin, R. Liang, J. Mitra, E. Fallon and Y. Chen, “Automatic Routability Predictor Development Using Neural Architecture Search,” IEEE/ACM International Conference on Computer-Aided Design, 2021.
166. Y. Lin, R. Liang, Y. Li, H. Hu and J. Hu, “Mapping Large Scale Finite Element Computing onto Wafer-Scale Engines,” ACM/IEEE Asia and South-Pacific Design Automation Conference, 2022.
167. Y. Lin, Y. Li, D. Fang, M. Madhusudan, S. S. Sapatnekar, R. Harjani and J. Hu, “Are Analytical Techniques Worthwhile for Analog IC Placement?” ACM/IEEE Design Automation and Test in Europe, 2022. (Best Paper Nominee)
168. D. Fang, B. Zhang, H. Hu, W. Li, B. Yuan and J. Hu, “Global Placement Exploiting Soft 2D Regularity,” ACM International Symposium on Physical Design, 2022.
169. G. Saumil, A. Tyagi, M. Quinn and J. Hu, “Transaction Level Stimulus Optimization in Functional Verification Using Machine Learning Predictors,” IEEE International Symposium on Quality Electronic Design, 2022.
170. J. Song, D. Porter, J. Hu and T. Marek, “Double Deep Q-Learning Based Irrigation and Chemigation Control,” IEEE International Symposium on Quality Electronic Design, 2022.
171. J. Pan, C.-C. Chang, Z. Xie, A. Li, M. Tang, T. Zhang, J. Hu and Y. Chen, “Towards Collaborative Intelligence: Routability Estimation based on Decentralized Private Data,” ACM/IEEE Design Automation Conference, 2022.
172. C.-W. Hu, J. Hu and S. Khatri, “TD3lite: FPGA Acceleration of Reinforcement Learning with Structural and Representation Optimizations,” International Conference on Field Programmable Logic and Applications, 2022.
173. R. Liang, H. Xiang, J. Jung, J. Hu and G.-J. Nam, “A Stochastic Approach to Handle Non-Determinism in Deep Learning-Based Design Rule Violation Predictions,” IEEE/ACM International Conference on Computer-Aided Design, 2022.
174. P. Sengupta, A. Tyagi, Y. Chen and J. Hu, “How Good is Your Verilog RTL Code? A Quick Answer from Machine Learning,” IEEE/ACM International Conference on Computer-Aided Design, 2022.
175. R. Liang, J. Song, B. Yuan and J. Hu, “Deep Learning Toolkit-Accelerated Analytical Co-optimization of CNN Hardware and Dataflow,” IEEE/ACM International Conference on Computer-Aided Design, 2022.
176. Z. Xie, S. Li, M. Ma, C.-C. Chang, J. Pan, Y. Chen and J. Hu, “DEEP: Developing Extremely Efficient Runtime On-Chip Power Meters,” IEEE/ACM International Conference on Computer-Aided Design, 2022.
177. J. Pan, C.-C. Chang, Z. Xie, J. Hu and Y. Chen, “Robustify ML-based Lithography Hotspot Detectors,” IEEE/ACM International Conference on Computer-Aided Design, 2022.
178. H. Hu, J. Hu, F. Zhang, B. Tian and I. Bustany, “Machine-Learning Based Delay Prediction for FPGA Technology Mapping,” ACM/IEEE Workshop on System Level Interconnect Pathfinding, 2022.
179. C.-C. Chang, J. Pan, Z. Xie, Y. Li, Y. Lin, J. Hu and Y. Chen, “Fully Automated Machine Learning Model Development for Analog Placement Quality Prediction,” ACM/IEEE Asia and South-Pacific Design Automation Conference, 2023. (Best Paper Nominee)
180. C.-C. Chang, J. Pan, Z. Xie, J. Hu and Y. Chen, “Rethink Before Releasing Your Model: ML Model Extraction Attack in EDA,” ACM/IEEE Asia and South-Pacific Design Automation Conference, 2023. (Best Paper Award)
181. R. Liang, S. Nath, A. Rajaram, J. Hu and H. Ren, “BufFormer: A Generative ML Framework for Scalable Buffering,” ACM/IEEE Asia and South-Pacific Design Automation Conference, 2023.
182. C. Fu, B. Trombley, H. Xiang, G.-J. Nam and J. Hu, “Machine Learning Techniques for Pre-CTS Identification of Timing Critical Flip-Flops,” IEEE Computer Society Annual Symposium on VLSI, 2023.
183. J. Hu, “Lightning Talk: Power and Performance Reconciliation – from Tradeoff to Win-Win,” ACM/IEEE Design Automation Conference, 2023. (Invited paper)
184. K. Bharathi, S. P. Khatri and J. Hu, “Scaled Population Division for Approximate Computing,” IEEE/ACM International Symposium on Low Power Electronics and Design, 2023.
185. Y. Lin, Y. Li, M. Madhusudan, S. S. Sapatnekar, R. Harjani and J. Hu, “MMM: Machine Learning-Based Macro-Modeling for Linear Analog ICs and ADC/DACs,” ACM/IEEE Workshop on Machine Learning for CAD, 2023. (Best Student Paper Award)
186. P. Sengupta, A. Tyagi, Y. Chen and J. Hu, “Early Identification of Timing Critical RTL Components using ML Based Path Delay prediction,” ACM/IEEE Workshop on Machine Learning for CAD, 2023.
187. Z. Wang, W. Shi, J. Hu and L. Xie, “A Parallel Approach for Solving Network Equations in EMT Simulation Based on Branch Partition,” North American Power Symposium, 2023.
188. E. S. Alcorta, A. Gerstlauer, C. Deng, Q. Sun, Z. Zhang, C. Xu, L. W. Wills, D. S. Lopera, W. Ecker, S. Garg, and J. Hu, “Machine Learning for Embedded System Design,” ACM/IEEE International Conference on Hardware/Software Codesign and System Synthesis, 2023. (Invited paper)
189. H. Hu, D. Fang, W. Li, B. Yuan and J. Hu, “Systolic Array Placement on FPGAs,” IEEE/ACM International Conference on Computer-Aided Design, 2023.
190. J. Song, R. Liang, Y. Gong, B. Yuan and J. Hu, “DiMO-Sparse: Differentiable Modeling and Optimization of Sparse CNN Dataflow and Hardware Architecture,” ACM/IEEE Design Automation and Test in Europe, 2024.
191. E. C. Barboza, M. Ketkar, P. V. Gratz and J. Hu, “Aiding Microprocessor Performance Validation with Machine Learning,” IEEE International Symposium on Performance Analysis of Systems and Software, 2024. (Best Paper Nominee)
192. P. Sengupta, V. K. Rajan, H. Mostafa, S. Majumdar, A. Tyagi, J. Hu, “MinBLoG: Minimization of Boolean Logic Functions using Graph Attention Network,” ACM/IEEE International Symposium on Machine Learning CAD, 2024. (Best Paper Award)
193. C. Roman-Vicharra, Y. Chen and J. Hu, “Flip-flop Centric Incremental Placement for Simultaneous Timing and Clock Network Power Optimization,” ACM/IEEE International Symposium on Machine Learning CAD, 2024.
194. D. Fang, H. Hu, W. Li, B. Yuan and J. Hu, “SysMix: Mixed-Size Placement for Systolic-Array-Based Hierarchical Designs,” IEEE/ACM International Conference on Computer-Aided Design, 2024.
195. C.-C. Chang, W.-H. Lin, J. Pan, G. Zhou, Z. Xie, J. Hu and Y. Chen, “PRICING: Privacy-Preserving Circuit Data Sharing Framework for Lithographic Hotspot Detection,” ACM/IEEE Asia and South-Pacific Design Automation Conference, 2025.
196. R. Wang, S. Kong, L. Wang, Y. Wang and J. Hu, “Automated Identification of Repeated Chip Layout Patterns,” SPIE Advanced Lithography and Patterning Symposium, 2025.
197. V. Chhabria, A. B. Kahng, J. Hu and S. S. Sapatnekar, “Invited: Toward an ML EDA Commons: Establishing Standards, Accessibility, and Reproducibility in ML-driven EDA Research,” ACM International Symposium on Physical Design, 2025.
198. G. Zhou, B. Korrapati, G. R. Reddy, C.-C. Chang, J. Pan, J. Hu, Y. Chen and D. G. Thakurta, “PatternPaint: Practical Layout Pattern Generation Using Diffusion-Based Inpainting”, ACM/IEEE Design Automation Conference, 2025.
199. Z. Wang, W. Shi and J. Hu, “FPGA-Based Acceleration for EMT Simulation of Electrical Distribution Network”, IEEE International Conference on Application-specific Systems, Architectures and Processors, 2025.
200. M. Luu, S. Jasper, K. Le, E. Pan, M. Quinn, A. Tyagi and J. Hu, “VCDiag: Classifying Erroneous Waveforms for Failure Triage Acceleration,” ACM/IEEE International Symposium on Machine Learning CAD, 2025.
201. S. Jasper, M. Luu, E. Pan, A. Tyagi, M. Quinn, J. Hu and D. K. Houngninou, “BugGen: A Self-Correcting Multi-Agent LLM Pipeline for Realistic RTL Bug Synthesis,” ACM/IEEE International Symposium on Machine Learning CAD, 2025.
202. C. Liu, J. P. Parlapalli, D. K. Houngninou, M. Quinn, A. Tyagi and J. Hu, “Improving Last-Mile Coverage in Functional Verification,” ACM/IEEE International Symposium on Machine Learning CAD, 2025.
203. Y. Gong, L. Huang, H. Chang, R. Liang, C. Yang, Z. Tang, J. Hu and Bo Yuan, “Crane: Inter-Layer Scheduling Framework for DNN Inference and Training Co-Support on Tiled Architecture,” IEEE/ACM International Symposium on Microarchitecture , 2025.
204. R. Wang, P. Sengupta, C. Roman-Vicharra, Y. Chen and J. Hu, “Lorecast: Layout-Aware Performance and Power Forecasting from Natural Language,” ACM/IEEE Asia and South-Pacific Design Automation Conference, 2026.
205. D. Fang, H. Hu, W. Li and J. Hu, “A New Approach to Performance-Driven Analog IC Placement,” ACM International Symposium on Physical Design, 2026.
206. R. Wang, J. Pan, Y. Chen and J. Hu, “AstroTune: AST-Assisted LLM Retrieval for Cross-Stage Design Flow Parameter Tuner,” ACM International Symposium on Physical Design, 2026.
207. A. Stickney, O. Castro, A. Chan, P. V. Gratz, J. Hu, A. Tyagi, J. Dominguez-Trujillo, G. Shipman and K. Sheridan, “Machine Learning-Driven Early Performance Prediction Framework for Accelerated Microarchitecture Simulation,” ACM/IEEE Design Automation and Test in Europe, 2026.
208. H. Hu, H. Chang, D. Fang, Z. Wang, W. Li, R. Liang, B. Yuan and J. Hu, “LegoMap: Optimization for High-Throughput Transformer Computing on AI Engine-Based FPGAs,” IEEE International Symposium on Field-Programmable Custom Computing Machines, 2026.
209. C. Roman-Vicharra, P. Sengupta, R. Wang, Y. Chen and J. Hu, “SMUFTA: Simultaneous Multi-die Floorplanning and Technology Assignment,” ACM/IEEE International Symposium on Machine Learning CAD, 2026. (Best Paper Nominee)
210. F. Wu, R. Wang, E. Pan, A. Tyagi, M. Quinn, D. Houngninou, JV Rajendran and J. Hu, “Spec2Assertion: Automatic Pre-RTL Assertion Generation by LLMs with Progressive Regularization,” ACM/IEEE International Symposium on Machine Learning CAD, 2026. (Best Paper Nominee)
211. R. Wang, D. Fang, G. Zhou, F. Wu, Y. Chen and J. Hu, “DREAM: Design-flow and RTL Enhancement via End-to-End LLM-Assisted Method,” ACM/IEEE International Symposium on Machine Learning CAD, 2026.
212. B. Schaible, A. S. Bharadwaj, U. Schlichtmann and J. Hu, “A Systolic Array Architecture for Nonlinear Activation Functions and Softmax Computation using Chebyshev Polynomials,” IEEE International Conference on Omni-Layer Intelligent Systems, 2026. (Best Paper Nominee)
213. H. Chang, H. Hu, Z. Wang, Y. Gong, R. Liang, Z. Tang, B. Yuan and J. Hu, “Fast Cross-Operator Optimization of Attention Dataflow on Spatial Accelerators,” IEEE/ACM International Conference on Parallel Architectures and Compilation Techniques, 2026.
214. Z. Wang, H. Chang, Y. Sui, R. Liang, B. Yuan and J. Hu, “SampKV: Saliency-Aware Mixed-Precision KV Cache for Efficient Diffusion Language Model Inference,” Conference on Empirical Methods in Natural Language Processing, 2026.
215. D. Fang, H. Hu, W. Li, G. Coraluppi, R. Wang and J. Hu, “GRASP: A Graph-Based Approach to Timing-Driven Systolic Array Placement on FPGAs,” IEEE/ACM International Conference on Computer-Aided Design, 2026.
216. C. Roman-Vicharra, D. Fang, H. Chang, C. Yu, Y. Chen and J. Hu, “PWaT3D-Planner: Bridging Power and Timing Optimization with Thermal-Mechanical Awareness,” IEEE/ACM International Conference on Computer-Aided Design, 2026.

Tutorial C. J. Alpert, J. Hu, N. Menezes and W. Shi, “Buffering interconnect: from basics to breakthroughs,” ACM/IEEE Design Automation Conference, San Diego, 2004.

Software Release
Statistical timing analysis with GPU acceleration, 2016.
Network flow attack tool in split manufacturing, 2017.
Post placement timing and power prediction from Verilog code, 2024.

SLICE: Shared machine Learning Infrastructure for the Community of EDA
NSF Workshop on Shared Infrastructure for Machine Learning EDA

Editor-in-Chief ACM Transactions on Design Automation of Electronic Systems, 2024 – present

Associate Editor
IEEE Transactions on CAD, 2006 -2011
ACM Transactions on Design Automation of Electronic Systems, 2011 – 2020
Integration: the VLSI Journal, 2013 – 2017

Guest Editor
IET Devices, Circuits and Systems, Special Issue on Design for Manufacturability, 2007
IEEE Transactions on CAD, 2012, 2014

Co-founder IEEE Texas Workshop on Integrated System Exploration (TexasWISE), 2012 — 2015

Best Paper Selection Committee Member
ACM Transactions on Design Automation of Electronic Systems, 2011
IEEE/ACM International Conference on Computer-Aided Design, 2013, 2014
ACM/IEEE Design Automation Conference, 2017

Best Paper Selection Committee Chair, ACM Transactions on Design Automation of Electronic Systems, 2013

ACM/SIGDA Outstanding PhD Dissertation Award Committee Member, 2013, 2014, 2015

IEEE/ACM IEEE 10 Year Impact Award Committee Member, 2021

Publicity Chair, ACM International Symposium on Physical Design, 2009

Publications Chair, ACM International Symposium on Physical Design, 2010

Technical Program Chair, ACM International Symposium on Physical Design, 2011

Technical Program Co-Chair, ACM/IEEE International Workshop on ML CAD, 2023

General Chair, ACM International Symposium on Physical Design, 2012

General Co-Chair, ACM/IEEE International Symposium on ML CAD, 2024

Steering Committee Chair, ACM International Symposium on Physical Design, 2013

Tutorial Organizer, ACM/IEEE Design Automation Conference, 2019

Panel Moderator, ACM/IEEE Design Automation Conference, 2020

Technical Program Track Chair

• ACM/IEEE Design Automation Conference, Physical Design and Manufacturability Track, 2008
• Asia and South-Pacific Design Automation Conference, Emerging Applications Track, 2019
• IEEE/ACM International Conference on Computer-Aided Design, Analog Track, 2022

Technical Program Committee Member

• IEEE International Conference on Computer Design (ICCD), 2001, 2002, 2011, 2012, 2013
• ACM International Symposium on Physical Design (ISPD), 2003, 2004, 2005, 2009, 2010, 2022
• IEEE International Symposium on Circuits and Systems (ISCAS), 2004, 2005, 2006
• IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2004, 2005, 2006, 2015, 2016, 2017, 2021
• ACM/IEEE Design Automation and Test at Europe (DATE), 2005, 2008, 2009, 2010
• ACM/IEEE Design Automation Conference (DAC), 2006, 2007, 2008, 2014, 2015, 2016, 2019, 2021, 2022
• IEEE International Symposium on Quality Electronic Design (ISQED), 2007, 2008, 2009
• IEEE Asia Symposium on Quality Electronic Design (ASQED), 2010
• Workshop on Synthesis and System Integration of Mixed Information Technologies (SASIMI), 2009
• ACM International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU), 2011
• IEEE/ACM International Conference on VLSI Design, 2013
• ACM/IEEE Asia and South Pacific Design Automation Conference (ASP-DAC), 2013, 2019
• ACM/IEEE International Symposium on Low Power Electronics Design (ISLPED), 2013, 2014, 2015
• ACM/IEEE Great Lake Symposium on VLSI (GLSVLSI), 2015
• IEEE International Conference on Autonomic Computing (ICAC), 2017
• International Symposium on VLSI Design, Automation and Test (VLSI-DAT), 2017, 2018
• AAAI Conference on Artificial Intelligence, 2021

Steering Committee Member

• ACM International Symposium on Physical Design (ISPD), 2017, 2018, 2019, 2020, 2021, 2022

Session Chair

• ACM/IEEE Asia and South Pacific Design Automation Conference, 2004, 2020
• IEEE/ACM International Conference on Computer-Aided Design, 2005, 2006, 2015, 2016, 2020
• ACM/IEEE Design Automation Conference, 2007, 2017, 2018, 2019, 2020
• ACM International Symposium on Physical Design, 2009, 2018, 2021
• IEEE International Conference on Computer Design, 2012, 2013, 2015
• ACM/IEEE International Symposium on Low Power Electronics Design 2014, 2015, 2023

Ph.D. Students

Zhenrui Wang (jointly advised by Prof. Shi)
Cristhian Roman Vicharra
Haodong Chang
Chengjia Liu (jointly advised by Prof. Tyagi and Prof. Quinn)
Benedikt Schaible (jointly advised by Prof. Ulf Schlichtmann)
Fenghua Wu (jointly advised by Prof. Tyagi and Prof. Quinn)
Yiyang Yan
Minh Luu (jointly advised by Prof. Tyagi and Prof. Quinn)
Guohao Dai
Anindya Choudhury

M.S. Students

Sushil Suresh Sumathi
Manoj Kumar Balamurugan
Zach Assad
Tasnia Jamal
Shou-En Liu
Joonhyun Choi
Habeeb Mohammed
Caster Yuan

Visiting Scholars

Ning Xu, Wuhan University of Technology, China
Youmeng Li, Tianjin University, China
Xinguo Deng, Fuzhou University, China
Wai-Kei Mak, National Tsinghua University, Taiwan

Visiting Graduate Students

Yujie Wang, Nankai University, China
Guan-Qi Fang, National Taiwan University of Science and Technology, Taiwan
Yu-Hung Huang, National Taiwan University of Science and Technology, Taiwan

Graduated Ph.D. Students

Chin-Ngai Sze (Cliff), 2005, IBM Austin Research Lab
Di Wu, 2006, Cadence
Ganesh Venkataraman, 2007, Magma
Ke Cao, 2007, Marvell
Shiyan Hu, 2008, Michigan Tech University (Faculty)
Rupak Samanta, 2008, Intel
Yifang Liu, 2009, Google
Kyu-Nam Shim, 2012, Intel
Xi Chen, 2013, Qualcomm
Jae-Yeon Won, 2015, Synopsys
Hao He, 2016, Thumbtack
Jiafan Wang, 2017, Synopsys
Chaofan Li, 2018, Synopsys
Justin Sun, 2018, Quicken Loans
He Zhou, 2019, Cadence
Wenbin Xu, 2019, Cadence
Lin Huang, 2019, Cadence
Yanxiang Yang, 2019, Amazon
Lang Feng, 2020, Nanjing University
Hongxin Kong, 2020, Cadence
Nithyashankari Jayasankaran, 2021, Qualcomm
Erick Carvajal Barboza, 2021, University of Costa Rica (Faculty)
Rongjian Liang, 2021, Nvidia
Yaguang Li, 2022, Nvidia
Yishuang Lin, 2023, Nvidia
Jianfeng Song, 2023, Siemens EDA
Prianka Sengupta, 2024, Nvidia
Hailiang Hu, 2025, AMD
Donghao Fang, 2026, Agentrys
Runzhi Wang, 2026, Synopsys

Graduated M.S. Students

Rishi Chaturvedi, 2004, Analog Devices Inc.
Anand Rajaram, 2004, Texas Instrument
Vikram Seth, 2004, Redpine Signals Inc.
Min-Seok Kim, 2006, Samsung Electronics
Qiuyang Li, 2006, Juniper Networks
Sridhar Varadan, 2007
Trenton Henrichson, 2008, AMD
Nimay Shah, 2008, Analog Devices Inc.
Carlos Esquit Hernandez, 2008, University of the Valley of Guatemala
Pratik Shah, 2008, Nvidia
Venkata Rajesh Mekala, 2010, Nvidia
Subodh Prabhu, 2010, Cisco
Tanuj Jindal, 2010, Intel
Amrinder Singh, 2010, Intel
Sundararajan Ramakrishnan, 2010, Intel
Yu Yang, 2011, Synopsys
Yi-Le Huang, 2011, Nvidia
Qiong Zhao, 2012, AMD
Alvin Chang, 2012, Intel
Zheng Xu, 2013, National Instruments
Jung-Tai Tsai, 2013, Xilinx
Farah Rasheed, 2013, JHU Applied Physics Lab
Ruixiao Ni, 2013, Marvell
Shalimar Rasheed, 2014, Nvidia
Gongming Yang, 2014, FactSet
Rohit Kumar, 2014, Nvidia
Chia-Yu Wu, 2015, Altera
Sitong Zhai, 2015
Shivaram Irukula, 2015, Intel
Ang Lu, 2015, Xilinx
Zhuoyang Gao, 2015, Amazon
Yiren Shen, 2016, Amazon
Rohit Gangrade, 2016, Apple
Pu Chen, 2016, Amazon
Nfn Shrija, 2016, Intel
Saumil Gogri, 2019, Cypress Semiconductor
Amrutha Shikaripura Jagadeesh, 2019, Intel
Abhijith Reddy, 2019, Marvell
Vaishnavi Venkatesh, 2019, Micron
Sanjay Rajashekar, 2020, Apple
Sara Jacob, 2020, NXP
John Muschinske, 2024
Giacomo Coraluppi, 2025, Toshiba-Mitsubishi Electric Industrial Systems Corporation

For Prospective Students

Roughly speaking, VLSI CAD is to develop software algorithms to assist VLSI circuit designs. This objective itself implies that both Electrical Engineering (EE) and Computer Science (CS) background are requested. Since the ultimate goal is to enable efficient and high performance circuit design, obviously you have to understand VLSI circuit design. As for the CS part, both algorithm design and proficient programming skill are essential because CAD research is somewhat equivalent to algorithm design and the effectiveness of the algorithms need to be verified through software implementations. Sometimes, advanced algorithm designs require knowledge in Applied Math such as linear programming, graph theory and combinatorial optimizations.

Ideally, it is preferred that you have background on all of the aforementioned fields: VLSI design, algorithms and applied math. However, this rarely happens for a junior graduate student. In practice, I wish you to have a solid background on at least one of these fields. As long as you are diligent and intelligent, you will be successful!