Focus Areas

My current research projects fall broadly under the three areas listed below. My research group’s activities have been funded via government (NSF, LLNL, NSA, NCMR, DNDO) as well as industrial (Intel, Nascentric, NSC, SRC, Accelicon, NVIDIA) sources.

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Some of the papers listed under the links on this page may appear in multiple links, based on their topics.

1. Computer Systems: In this category, my work falls into two subcategories.
   1. The first is computer architecture from the circuits up (including the design of efficient NoCs using a resonant clocking as well as a superposition-of-sinusoids paradigm, special function units for comparison, hashing, logarithm/antilogarithm computation, cryptographic key generation, Boolean Satisfiability and sorting, low energy and low power design using sub-threshold circuits, system prototyping, specialized architectures for arithmetic circuits, radiation tolerance/detection, as well as circuit and architectural approaches for resilience, crosstalk avoidance, clocking, leakage reduction and testability. My group also develops system prototypes to validate our ideas – for example, in extreme low power/energy computation, architectures for cryptography and FPGA based architectures for Boolean Satisfiability).
      • Network-on-Chip and Special Function Units (ongoing)
      • Extreme Low Power/Energy System Design (ongoing)
      • New Architectures for Arithmetic Circuits (ongoing)
      • Radiation and Process Variation Tolerance (ongoing)
      • Clocking in VLSI Design (ongoing)
      • Controlling On-chip (Capacitive) and Off-chip (Inductive) Crosstalk (past)
      • Testing and ATPG (past)
      • Leakage Reduction and Modeling (past)
   2. The second sub-category consists of algorithm acceleration (using GPUs, FPGAs and custom ICs), for algorithms in the VLSI CAD (for fault simulation, logic simulation, circuit simulation, fault table generation, SAT), radar signal processing (for weather radar), cryptography and communications (LDPC decoders, MIMO decoders, WiMAX decoders) domains.
      • Algorithm Acceleration with GPUs, FPGAs and Custom ICs (ongoing)
2. Logic and its applications: In this area, my work initially started in the space of logic synthesis for VLSI CAD. In the last couple of years, I have directed this work towards genomics (predictor inference, Gene Regulatory Network (GRN) construction, determining optimal drug regime for a genetic disease), noise based logics and their realization, and Boolean Satisfiability solvers (using noise based logic as well as GPU, FPGA and custom IC based accelerators).
   • Logic Techniques Applied to Genomics (ongoing)
   • Boolean Satisfiability (ongoing)
   • Noise-based Logic (ongoing)
   • Logic Synthesis (past)
3. Interdisciplinary extensions: The above two areas form a spring-board from which I engage in research in other domains. I explore extensions of the above two areas to other areas such as IP routing (routing table compression, architecture and design of Ternary CAMs), Digital Signal Processing (architectures and designs for FFT, FPGA and GPU based radar signal processors), optical networking (SAT based Routing and Wavelength Assignment for DWDM optical networks), wireless communication (MIMO decoders, WiMAX decoders) and coding (LDPC decoders, fix-free code generators).
   • Interdisciplinary Extensions (ongoing)

Ph.D.

University of California, Berkeley. Department of Electrical Engineering and Computer Sciences. (1993 – 99). Awarded the California MICRO Fellowship, 1993-94. Maintained a GPA of 3.963.

M. S.

University of Texas, Austin. Department of Electrical and Computer Engineering (1987 – 89). Awarded the Microelectronics and Computer Development (MCD) Fellowship, 1987-89). Maintained a GPA of 3.909.

B. S.

Indian Institute of Technology, Kanpur, India. Department of Electrical Engineering (1983 – 87). Obtained a GPA of 3.72, ranked fourth in a class of sixty students.

Dissertation/Thesis

Ph. D.

“Cross-talk Noise Immune VLSI Design using Regular Layout Fabrics”. Committee: Professor R. K. Brayton (Co-chair), A. Sangiovanni-Vincentelli (Co-chair) and Professor Dorit Hochbaum, University of California, Berkeley.

M. S.

“The Design of the METRIC Memory Interface and Memory System”. This involved the design of the memory interface of METRIC, a multi-threaded RISC Microprocessor. Sunil P. Khatri Page 3 of 50 Committee: Professor M. Ray Mercer (chair) and Professor Donald Fussell, University of Texas at Austin.

B. S.

Senior project involved implementing graphics algorithms on a MC68000-based terminal. Advisor: Professor A Joshi, Indian Institute of Technology, Kanpur, India.

My research covers 3 broad areas. The first is Computer Systems including computer architecture from the circuits up, and algorithm acceleration using GPUs, FPGAs and custom ICs. The second is Logic and its Applications, while the third area consists of Interdisciplinary Extensions of the first two. Note: The artefacts listed below may not be up to date. For the latest listing of artefacts, please see my vitae.

• • 1. “A Sum-Of-Product Based Multiplication Approach For FIR Filters And DFT”, Kumar, Khatri. Monograph published by LAP LAMBERT Academic Publishing. 1st edition, January 2014. 64p. ISBN 978-3-8484-8636-6.
    2. “Source-Synchronous Networks-On-Chip: Circuit and Architectural Interconnect Modeling”, Mandal, Khatri, Mahapatra. Monograph published by Springer Publishers. 1st edition November 2013. 160p. ISBN 978-1-4614-94041.
    3. “Logic Synthesis for Genetic Diseases: Modeling Disease Behavior Using Boolean Networks”, Lin, Khatri. Monograph published by Springer Publishers. 1st edition, November 2013. 140p. ISBN 978-1-4614-9428-7.
    4. ”Practical & Real Time IP Routing Table Compression – Extending algorithms from digital logic synthesis”. Bollapalli, Khatri. Published by LAP Lambert Academic Publishing, Jan 2012, pp 68. ISBN 978-3847321521
    5. ”Advanced Techniques in Logic Synthesis, Optimizations and Applications”, Khatri, Gulati, editors. Springer Publishers, 1st ed, 2011. 240p. ISBN 978-1-4419-7517-1
    6. ”Robust Window-Based Multi-node Minimization Technique Using Boolean Relations”, Cobb, Gulati, Khatri. pp 309-333, In ”Advanced Techniques in Logic Synthesis Optimizations and Applications”, Khatri, Gulati, ed. Springer Publishers.
    7. ”Digital Logic Using Non-DC Signals” Bollapalli, Khatri, Kish. pp 383-400. In ”Advanced Techniques in Logic Synthesis Optimizations and Applications”, Khatri, Gulati, ed. Springer Publishers.
    8. ”On and Off-chip Cross-talk Avoidance in VLSI Designs”, Duan, LaMeres, Khatri. Monograph published by Springer Publishers. 1st edition, 2010. 240p. ISBN 978-1-4419-0946-6.
    9. ”EDA Algorithm Acceleration with FPGAs, GPUs, and Custom ICs”, Gulati, Khatri. Monograph published by Springer Publishers. 1st edition, 2010. 194p. ISBN 978-1-4419-0943-5
    10. ”Analysis and Design of Resilient VLSI Circuits: Mitigating Soft Errors and Process Variations”, Garg, Khatri. Monograph published by Springer Publishers. 1st edition, 2010. 212p. ISBN 978-1-4419-0930-5
    11. ”Minimizing and Exploiting Leakage in VLSI Design”, Jayakumar, Paul, Garg, Khatri. Monograph published by Springer Publishers. 1st edition, 2010. 214p. ISBN 978-1-4419-0949-7.
    12. Invited chapter ”Logic Synthesis” in the CRC EDA handbook ”EDA for IC Implementation, Circuit Design and Process Technology”. Editors L. Lavagno, L. Scheffer, G. Martin. ISBN 0849379245, 9780849379246, 571pp, published 2006. Chapter co-authored by Narendra Shenoy of Synopsys Inc. The wikipedia entry on ”Logic Synthesis” is based on the material in this chapter.
    13. ”Cross-talk Noise Immune VLSI Design using Regular Layout Fabrics”, Khatri, Brayton, Sangiovanni-Vincentelli. Research Monograph published by Kluwer Academic Publishers. ISBN # 0-7923-7407-X.

• • 1. ”Noise-based Computation”, Bezrukov, Gingl, Horvath, Kish, Khatri, Peper. Contract for this Research Monograph submitted to Springer Publishers. The book is expected to be published in 2012
    2. ”VLSI Design from the Middle Out” Khatri, Gerosa. Contract for this electronic textbook on VLSI design approved by Springer Publishers. This book is expected to be published in 2013.
    3. ”Logic Synthesis applied to Genetic Disease Modeling and Cure”, Lin, Khatri. Contract for this brief research monograph submitted to Springer Publishers. The brief is expected to be published in 2012.
    4. ”Resonant Clocking and its Applications”, Cordero, Karkala, Mandal, Khatri. Contract for this brief research monograph submitted to Springer Publishers. The brief is expected to be published in 2012.

• • 1. ”Introduction to GPU Programming for EDA”, Croix, Khatri. This tutorial was presented at the International Conference on Computer-Aided Design (ICCAD), San Jose, CA, Nov. 2-5, 2009.
    2. ”Structured ASIC Design Approaches and Trends”, Technical Forum, DesignCon East, Worcester, MA, Sep 19-21, 2005.

• • 1. “Challenges and Opportunities of Stochastic Computing in the Dusk of Moore’s Law and the Dawn of Big Data”, Invited to serve on a panel at the IEEE/ACM International Conference on Computer-Aided Design (ICCAD), Nov 7-10, 2016, Austin, TX. Declined due to health reasons.
    2. “ Looking Beyond Moore’s Law”, Invited to serve on a panel at the IEEE Texas Workshop on Integrated System Integration (TexasWISE) 2016, Houston, TX.
    3. “Models and High-Speed Simulation”. Invited to Chair a Panel Session to discuss this topic, at the 15th ACM/IEEE System Level Interconnect Prediction (SLIP) Workshop 2013, Austin, TX. June 2, 2013.
    4. “Multi-core and GPU based Parallelism”. Invited to serve as a panelist to discuss this topic, along with leading academic and industry practitioners in this area. The panel was part of the IEEE CTS CAS/SSC/CEDA Workshop on Data Parallelism for Multi-core Chips and GPUs”, Austin, TX. October 5, 2012. My talk was titled  “Algorithm Acceleration for GPU Architectures”.
    5. ”Manycore, Heterogenous, or Neither: Which One is the Way to Go for EDA?”. Invited to serve as a panelist to discuss this topic, along with other leading researchers in the field of GPU based implementation of EDA algorithms. The panel was part of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD), San Jose, CA, Nov 7-10, 2011.
    6. ”The Top of Testing’s Most Wanted List – What is the most critical Testing challenge? (or have all the bad guys been caught already?)”, invited panelist (along with Jason Doege, T.M. Mak, Rob Dassch, Tom Williams and Luis Basto, some leading researchers in VLSI testing). This panel was part of the International Test Synthesis Workshop (ITSW) 2007, San Antonio, TX, March 5-7, 2007.
    7. ”Are we Fighting a Losing Battle, Dealing with Numerous and Complex Defects?”, invited to serve as a panelist along with 3 leaders in the field. Peer panelists were Dr. Tom Williams (Synopsys), Prof. Melvin Bruer (USC), and Al Crouch (Inovys Corporation). The panel was part of the International Test Synthesis Workshop (ITSW) 2006, Santa Barbara, CA, April 9-12, 2006.

Note: These papers are re-listed along with regular papers in a later section. They are separately listed here for ease of perusal.

• • 1. Invited chapter “A GPU-based Implementation of a Receding Horizon Sensor Tracking Methodology”, Abusultan, Chakravorty, Khatri. Invited to publish as a chapter in the Elsevier book “Advances in GPU Research and Practice”, H. Sarbazi-Azad (Editor).
    2. Invited chapter “GPU-based Algorithms in Electronic Design Automation”, Gulati, Khatri, Croix. Invited to publish as a chapter in the Elsevier book “Advances in GPU Research and Practice”, H. Sarbazi-Azad (Editor).
    3. Invited paper, “Information, noise and energy dissipation: Laws, limits and applications”, Kish, Granqvist, Khatri, Sundqvist, Peper Plenary talk at International Workshop on Molecular Architectonics, Shiretoko, Hokkaido, Japan, August 3-6, 2015.
    4. Invited paper “”Demonic” challenge: Landauer’s erasure-dissipation” Kish, Granqvist, Khatri. 44th Winter Colloquium on the Physics of Quantum Electronics (PQE) 2014, Snowbird, UT. January 5-9, 2014.
    5. Invited paper “Demons: Maxwell demon; Szilard engine; and Landauer’s erasure-dissipation”, Kish, Granqvist, Khatri, Wen. Hot Topic of Physical Informatics (HoTPI) 2013, November 10-13, Changsha, China. November 10-13, 2013.
    6. Invited paper, “Using GPUs to Accelerate CAD Algorithms”, Croix, Gulati, Khatri. IEEE Design & Test, Vol. 30, Issue 1. February 2013, pp 8-16.
    7. Invited paper, “Algorithm Acceleration for GPU Architectures”, IEEE CTS CAS/SSC/CEDA Workshop on Data Parallelism for Multi-Core Chips and GPUs, Austin, TX. October 5, 2012.
    8. Invited paper, “Application of logic synthesis to the understanding and cure of genetic diseases”, Lin, Khatri. IEEE/ACM Design Automation Conference (DAC) 2012, San Francisco, CA. June 3-7, 2012, pp 734-740.
    9. Invited paper, “Noise-based Information Processing”, Kish, Khatri, Bezrukov, Peper, Gingl, Horváth. 21st International Conference on Noise and Fluctuations. June 12-16 2011, Toronto, Canada. June 12-16, 2011, pp 28-33.
    10. Invited paper “DFM-Aware Structured ASIC Design”, Gopalani, Garg, Khatri. International Symposium on Integrated Circuits (ISIC) 2009, Singapore. December 14-16, 2009, pp 29-32.
    11. Invited paper “A PTL based Highly Testable Structured ASIC Design Approach”, Gulati, Jayakumar, Khatri. International Symposium on Integrated Circuits (ISIC) 2009, Singapore. December 14-16, 2009, pp 33-36.
    12. Invited paper “Highly Parallel Decoding of Space-Time Codes on Graphics Processing Units”, Bollapalli, Wu, Gulati, Khatri, Calderbank. Annual Allerton Conference on Communication, Control and Computing, 2009, Urbana, IL. September 30 – October 2, 2009, pp 1262-1269.
    13. Invited Paper, ”Noise-based logic and computing: what do we have so far?”, Kish, Khatri, Bezrukov, Peper, Gingl, Horvath. 21st International Conference on Noise and Fluctuations. June 12-16 2011, Toronto, Canada.
    14. Invited Paper ”DFM-Aware Structured ASIC Design”, Gopalani, Garg, Khatri. International Symposium on Integrated Circuits (ISIC) 2009, Singapore. December 14-16, 2009.
    15. Invited Paper ”A PTL based Highly Testable Structured ASIC Design Approach”, Gulati, Jayakumar, Khatri. International Symposium on Integrated Circuits (ISIC) 2009, Singapore. December 14-16, 2009.
    16. Invited Paper ”Highly Parallel Decoding of Space-Time Codes on Graphics Processing Units”, Bollapalli, Wu, Gulati, Khatri, Calderbank. Annual Allerton Conference on Communication, Control and Computing, 2009, Urbana, IL. Sept 30 – Oct 2, 2009.
    17. Invited Paper ”Noise-based logic and computing: from Boolean logic gates to brain circuitry and its possible hardware realization”, Kish, Bezrukov, Khatri, Gingl, Sethuraman. International Workshop on Natural Computing (IWNC) 2009, Himeji, Japan. September 23-25, 2009.
    18. Invited Paper ”Extreme Low Power Computing using Sub-threshold Circuits”, Segundo Magno Congreso Interancional del CIC 2007, Mexico City, Mexico, November 6-8, 2007
    19. Invited paper ”A Routing Technique for Structured Designs which Exploits Regularity”. Khatri, Das. VLSI Design and Test Workshop (VDAT-2001), Aug 2001.
    20. Invited paper ”Multi-valued Logic Synthesis”- Brayton, Khatri. 12th International Conference on VLSI Design (VLSI-99), pp 196-205, Goa, India, pp. 196-205.

• • 1. “Comparing Leakage Reduction Techniques for an Asynchronous NoC Router ” Fairouz, Abusultan, Elshennawy, Khatri. Journal of Low Power Electronics (JOLPE). Accepted for publication, to appear.
    2. “A GPU-CPU heterogeneous algorithm for NGS read alignment “, Al Kawam, Khatri, Datta. International Journal of Computational Biology and Drug Design, Vol 11, No 1-2, pp 52-66, 2018.
    3. “A Survey of Software and Hardware Approaches to Performing Read Alignment in Next Generation Sequencing “, Al-Kawam, Khatri, Datta. IEEE/ACM Transactions on Computational Biology and Bioinformatics, vol 14(6), pp 1202-1213, Nov-Dec 2017.
    4. “FTCAM: An Area-Efficient Flash-Based Ternary CAM Design “, Fedorov , Abusultan, Khatri. IEEE Transactions on Computers. Vol 65, issue 8, pp 2652-2658, Aug 2016.
    5. “Response to “Comment on ‘Zero and negative energy dissipation at information-theoretic erasure’” , Kish, Granqvist, Khatri, Peper. Accepted for publication in Journal of Computational Electronics. Vol 15, Issue 1, pp 343-346. Mar 2016.
    6. “Zero and negative energy dissipation at information theoretic erasure “, Kish, Granqvist, Khatri, Peper. Journal of Computational Electronics, 15(1), pp 335-339, Mar 2016.
    7. “Demons: Maxwell’s Demon, Szilard’s Engine and Landauer’s Erasure-dissipation ”, Kish, Granqvist, Khatri, Wen. International Journal of Modern Physics: Conference Series 33 (2014) 1460364-1 to 1460364-5.
    8. “Simulation Analysis of Scintillation in a NaI Detector”, Shah, Marianno, Khatri, Boyle. Journal of the Institute of Nuclear Materials Management (JNMM), Vol. 43, No. 1, Bonus content, 2014.
    9. “List Mode with the ORTEC digiBASE-E” , Hearn , Marianno, Khatri, Gypp.  In Health Physics: The Radiation Safety Journal, Vol. 106, Issue 2, February 2014, pp S12-S15.
    10. Invited paper,  “Using GPUs to Accelerate CAD Algorithms “, Croix, Gulati, Khatri. IEEE Design & Test, Vol. 30, Issue 1. February 2013, pp 8-16.
    11. “On Optimal and Achievable Fix-Free Codes”,  Savari, Yazdi , Abedini , Khatri. IEEE Transactions on Information Theory 58(8): 5112-5129, 2012.
    12. “Application of Max-SAT-based ATPG to optimal cancer therapy design “, Lin, Khatri. BMC Genomics 2012, 13 (Suppl 6):S5, 26 October, 2012.
    13. ‘A DCVSL Delay Cell for Fast Low Power Frequency Synthesis Applications”, Turker, Khatri, Sanchez-Sinencio. IEEE Transactions On Circuits and Systems – I, vol 58 number 6, June 2011. pp 1225-1238.
    14. ”Computation using Noise-based Logic: Efficient String Verification over a Slow Communication Channel”, Kish, Khatri, Horvath. European Journal of Physics B 79 (2011). pp 85-90.
    15. ”Noise-based deterministic logic and computing: a brief survey”, Kish, Khatri, Bezrukov, Peper, Gingl, Horvath. International Journal of Unconventional Computing 7, Feb 2011. pp 101-113.
    16. ”A Simultaneous Input Vector Control and Circuit Modification Technique to Reduce Leakage with Zero Delay Penalty”, Jayakumar, Khatri. ACM Transactions on Design Automation of Electronic Systems, 2010.
    17. ”Towards brain-inspired computing”, Gingl, Khatri, Kish. Fluctuation and Noise Letters 9 (2010). pp 403 – 412.
    18. ”Instantaneous noise-based logic”, Kish, Khatri, Peper. Fluctuation and Noise Letters 9 (2010). pp 323 – 330.
    19. ”Fault Table Computation on GPUs”, Gulati, Khatri. Journal of Electronic Testing: Theory and Applications (JETTA). Vol 26, number 2, April 2010. pp 195-209.
    20. ”Selective Forward Body Bias for High Speed and Low Power SRAMs”, Bollapalli, Garg, Gulati, Khatri. Accepted for publication at the Journal of Low Power Electronics (JOLPE), Vol. 5, No. 2, August 2009.
    21. ”Encoding Serial Data for Graphical EDP/Energy Minimization”, Ekambavananan, Garg, Khatri. Accepted for publication at the Journal of Low Power Electronics (JOLPE), Vol. 5, No. 2, August 2009.
    22. ”Noise-based Logic Hyperspace with the Superposition of 2^^N States in a Single Wire”. Kish, Khatri, Sethuraman. Physics Letters A. Vol 373, number 22, May 2009. pp 1928-1934.
    23. ”FPGA-Based Hardware Acceleration for Boolean Satisfiability”, Gulati, Paul, Khatri, Patil, Jas. ACM Transactions on Design Automation of Electronic Systems (TODAES). Vol 14, number 2, Mar 2009. Among the top 10 downloaded papers for the journal in 2010. Nominated for best paper for the journal (2010).
    24. ”Circuit-level Design Approaches for Radiation-hard Digital Electronics”, Garg, Jayakumar, Khatri, Choi. IEEE Transactions on Very Large Scale Integration Systems, vol 17, number 6, Jun 2009. pp 781-792.
    25. ”Efficient On-Chip Crosstalk Avoidance CODEC Design”, Duan, Cordero, Khatri. IEEE Transactions on Very Large Scale Integration Systems, vol 17, number 4, April 2009. pp 551-560.
    26. ”A Fast Hardware Approach for Approximate, Efficient Logarithm and Antilogarithm Computations”, Paul, Jayakumar, Khatri. IEEE Transactions on Very Large Scale Integration Systems, vol. 17, number 2, Feb 2009, pp. 269-277.
    27. ”Resource Sharing among Mutually Exclusive Sum-of-Product Blocks for Area Reduction”, Das, Khatri. ACM Transactions on Design Automation of Electronic Systems (TODAES), vol. 13, number 3, July 2008, pp. 51:1-51:7.
    28. ”An Efficient, Scalable Hardware Engine for Boolean Satisfiability and Unsatisfiable Core Extraction”, Gulati, Waghmode, Khatri, Shi. IET Computers and Digital Techniques, vol. 2, number 3, May 2008, pp. 214-229.
    29. ”A Probabilistic Method to Determine the Minimum Leakage Vector for Combinational Designs in the Presence of Random PVT Variations”, Gulati, Jayakumar, Khatri, Walker. Integration, the VLSI Journal, vol. 41, number 3, May 2008, pp. 399-412.
    30. ”SAT-based ATPG using Multi-level Compatible Don’t-Cares”, Gulati, Saluja, Khatri. ACM Transactions on Design Automation of Electronic Systems (TODAES), vol. 13, number 2, April 2008, pp. 24:1-24:18.
    31. ”A Dynamically De-skewable Clock Distribution Methodology”, Jayakumar, Kapoor, Khatri. IEEE Transactions on Very Large Scale Integration (TVLSI), vol. 16, number 9, Sept 2008, pp. 1220-1229.
    32. ”A Timing-Driven Approach to Synthesize Fast Barrel Shifters”, Das, Khatri. IEEE Transactions on Circuits and Systems II (TCAS-II), vol. 55, number 1, Jan 2008, pp. 31-35.
    33. ”A Novel Hybrid Parallel-Prefix Adder Architecture with Efficient Timing-Area Characteristic”, Das, Khatri. IEEE Transactions on Very Large Scale Integration, vol. 16, number 3, March 2008, pp. 326-331.
    34. ”A Predictably Low Leakage ASIC Design Style”, Jayakumar, Khatri. IEEE Transactions on Very Large Scale Integration, vol. 15, number 3, March 2007, pp. 276-285.
    35. ”Polymer Sensors to Monitor Roach Locomotion”, Lee, Cooper, Mika, Clayton, Garg, Gonzalez, Vinson, Khatri, Liang. IEEE Sensors Journal, vol. 7, number 12, Dec 2007, pp 1698-1702.
    36. ”High-throughput VLSI Implementations of Iterative Decoders and Related Code Construction Problems”. Nagarajan, Laendner, Jayakumar, Milenkovic, Khatri. Springer Journal of VLSI Signal Processing, vol 49, number 1, Oct 2007, pp 185-206.
    37. ”SPFD-based Wire Removal in Standard-cell and Network-of-PLA Circuits”- Khatri, Sinha, Brayton, Sangiovanni-Vincentelli. IEEE Transactions on Computer-Aided Design of Circuits and Systems, vol 23, number 7, June 2004, pp 1020-1030.
    38. ”An Efficient and Regular Routing Methodology for Datapath Designs Using Net Regularity Extraction”. Das, Khatri. Short paper, IEEE Transactions on CAD, Vol 21, Number 1. Special issue on Physical Design, Jan 2002, pp 93-101.

• • 1. “A Homomorphic Encryption Scheme Based on Affine Transforms “, Loyka, Zhou, Khatri. Proceedings of the 2018 ACM Great Lakes Symposium on VLSI (GLSVLSI), May 23-25, 2018, Chicago, IL. pp 51-56.
    2. “An FPGA-based Coprocessor for Hash Unit Acceleration ” Fairouz, Khatri. The 35th IEEE International Conference on Computer Design (ICCD). Nov 5-8, 2017, Boston, MA, pp 301 –304.
    3. “Fast, Ring-Based Design of 3D Stacked DRAM “, Douglass, Khatri. The 35th IEEE International Conference on Computer Design (ICCD) 2017, Nov 5-8, 2017, Boston, MA, pp 665-672.
    4. “Fast and Highly Scalable Bayesian MDP on a GPU Platform” , Zhou, Khatri, Hu, Liu, Sze. 8th ACM Conference on Bioinformatics, Computational Biology, and Health Informatics, 2017. Boston, MA, Aug 20-23 2017. Pp 158-167.
    5. “SAT-Based Optimization for Flash-Based Digital Designs” , Abusultan, Khatri. IEEE/ACM Design Automation Conferenece (DAC), Jun 18-22 2017, Austin, TX.
    6. “Architectural Simulations of a Fast, Source-synchronous Ring-based Network-on-chip Design”, Khatri, Mandal. 2017 AFCEA Autonomous Networking Technology Symposium (ANTS), June 13-14, Utica, NY.
    7. “Design of a Flash-based Circuit for Multi-valued Logic” , Abusultan, Khatri. Proceedings of the Great Lakes Symposium on VLSI (GLSVLSI) 2017, pp 41-46, May 10-12, 2017. Banff, Canada. 24.4% acceptance rate.
    8. “Circuit Level Design of a Hardware Hash Unit for use in Modern Microprocessors” , Fairouz, Abusultan, Khatri. Proceedings of the Great Lakes Symposium on VLSI (GLSVLSI) 2017, pp 101-106, May 10-12, 2017. Banff, Canada. 24.4% acceptance rate.
    9. “A Robust C-element Design with Enhanced Metastability Performance” , Sharma, Khatri. Proceedings of the Great Lakes Symposium on VLSI (GLSVLSI) 2017, pp 95-100, May 10-12, 2017. Banff, Canada. 24.4% acceptance rate. Best Paper Candidate.
    10. “A Flash-based Digital Circuit Design Flow “, Abusultan, Khatri. IEEE/ACM International Conference on Computer-Aided Design (ICCAD) 2016, Austin, TX, Nov 2016.
    11. “A GPU-CPU Heterogeneous Algorithm for NGS Read Alignment” , Al Kawam, Khatri Datta. International Conference on Intelligent Biology and Medicine (ICIBM), Houston, TX, November 2016.
    12. “A Practical Methodology to Validate the Statistical Behavior of Bloom Filters “, Kottapalli, Khatri. International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS) 2016, Pittsburgh, PA, Oct 2016.
    13. “Implementing low power digital circuits using flash devices “, Abusultan, Khatri. 2016 IEEE 34th International Conference on Computer Design (ICCD), pp 109-116, Oct 3-5, 2016, Phoenix, AZ.
    14. “A novel hardware hash unit design for modern microprocessors” , Fairouz, Abusultan, Khatri. 2016 IEEE 34th International Conference on Computer Design (ICCD). pp 412-415, Oct 3-5, 2016, Phoenix, AZ.
    15. “Exploring static and dynamic flash-based FPGA design topologies “, Abusultan, Khatri. 2016 IEEE 34th International Conference on Computer Design (ICCD), pp 416-419, Oct 3-5, 2016, Phoenix, AZ.
    16. “A Ternary-valued, Floating Gate Transistor-based Circuit Design Approach” , Abusultan, Khatri. IEEE International Symposium on VLSI (ISVLSI) 2016, Pittsburgh, PA. July 11-13, 2016, pp 719-724.
    17. “A GPU-based Implementation of a Sensor Tasking Methodology “, Chakravorty, Abusultan, Khatri. International Conference on Information Fusion (FUSION 2016), Heidelberg, Germany, July 5-8, 2016, pp 1398-1405.
    18. “Exploring Flash Devices to Implement Digital Circuits “, Abusultan, Khatri. IEEE/ACM Design Automation Conference (DAC), June 2016, Austin, TX.
    19. “The Neutron Detector Using Radiation Integrated Circuits ,” Shah, Marianno, Khatri; 2016 IEEE Symposium on Radiation Measurements and Applications, Berkeley, CA, May 22-26, 2016.
    20. “GPU acceleration for Bayesian control of Markovian genetic regulatory networks “, Zhou, Hu, Khatri, Liu, Sze, Yousefi. Workshop on Bioinformatics for Precision Medicine (held in conjunction with the International Conference on Health Informatics (BHI)) 2016), Las Vegas, NV, February 2016. pp 304-307.
    21. “Exploring the viability of stochastic computing”, de Aguilar, Khatri. International Conference on Computer Design (ICCD), New York City, NY, Oct 19-21, 2015. pp 391-394.
    22. “Critical Remarks on Landauer’s theorem of erasure dissipation and the related issues of the molecular engines: Maxwell-demon and Szilard-engine “, Kish, Granqvist, Khatri, Smulko, 23rd International Conference on Noise and Fluctuations (ICNF 2015), Xian, China, June 2-5, 2015.
    23. “An Efficient Approach to Sample On-Chip Power Supplies”,  Murray, Khatri. ACM Great Lakes Symposium on VLSI, Pittsburgh, PA, May 20-22, 2015, pp 241-244. Sunil P. Khatri Page 13 of 50
    24. “Delay, Power and Energy Tradeoffs in Deep Voltage-scaled FPGAs”,  Abusultan, Khatri. ACM Great Lakes Symposium on VLSI, Pittsburgh, PA, May 20-22, 2015, pp 111-114.
    25. “An Asynchronous Network-on-Chip Router with Low Standby Power ”, Elshennawy, Khatri. Accepted at the 32nd IEEE International Conference on Computer Design (ICCD), Seoul, Korea. October 19-22, 2014. Acceptance rate 31.1%. To appear.
    26. “An Area-efficient Ternary CAM Design using Floating Gate Transistors ”, Fedorov , Abusultan, Khatri. Accepted at the 32nd IEEE International Conference on Computer Design (ICCD), Seoul, Korea. October 19-22, 2014, pp55-60. Acceptance rate 31.1%.
    27. “Simulation Analysis of Scintillation in a NaI Detector” , Shah , Marianno, Khatri, Boyle. Accepted at 55th Annual Meeting of the Institute of Nuclear Materials Management (INMM), Atlanta, GA. July 20-24, 2014. Best paper award, Nonproliferation and Arms Control division.
    28. “Look-up Table Design for Deep Sub-threshold through Full-supply Operation ”, Abusultan, Khatri. Accepted at the 22nd IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM), Boston, MA. May 11-13, 2014, pp 259-266. Acceptance rate 16.4%.
    29. “A Comparison of FinFET based FPGA LUT Designs ”, Abusultan, Khatri. ACM/IEEE Great Lakes Symposium on VLSI Systems (GLSVLSI) 2014, Houston, TX. May 21-23, 2014. pp 353-358.
    30. “FPGA LUT Design for Wide-band Dynamic Voltage and Frequency Scaled Operation ”, Abusultan, Khatri, 22nd ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA) 2014, Monterey, CA. February 25-28, 2014.
    31. Invited paper “”Demonic” challenge: Landauer’s erasure-dissipation ” Kish, Granqvist, Khatri. 44th Winter Colloquium on the Physics of Quantum Electronics (PQE) 2014, Snowbird, UT. January 5-9, 2014.
    32. “Techniques to Improve the Efficiency of SAT Based Path Delay Test Generation “, Bian , Walker, Khatri. 27th International Conference on VLSI Design (2014), Mumbai, India. January 5-9, 2014, pp 50-55.
    33. Invited paper “Demons: Maxwell demon; Szilard engine; and Landauer’s erasure-dissipation “,Kish, Granqvist, Khatri, Wen. Hot Topic of Physical Informatics (HoTPI) 2013, Changsha, China. November 10-13, 2013.
    34. “Noise-based algorithms for functional equivalence and tautology checking”,  Lin, Khatri. 31st IEEE International Conference on Computer Design (ICCD) 2013, Asheville, NC. October 6-9, pp 235-240.
    35. “A low-jitter phase-locked resonant clock generation and distribution scheme”,  Mandal, Bollapalli, Jayakumar, Khatri, Mahapatra. 31st IEEE International Conference on Computer Design (ICCD) 2013, Asheville, NC. October 6-9, 2013, pp 487-490.
    36. “Mixed structural-functional path delay test generation and compaction”, Bian , Walker, Khatri, Lahiri . IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) 2013, New York City, NY. October 2-4, 2013, pp 7-12.
    37. “Solving the SAT Problem Using Noise-Based Logic on FPGAs “, Belsare, Elshennawy, Khatri.IEEE/ACM Design Automation Conference (DAC) 2013, Austin, TX. June 2-6, 2013.
    38. “FPGA LUT Design for Wide-Band Dynamic Voltage and Frequency Scaled Operation “, Abusultan, Khatri. IEEE/ACM Design Automation Conference (DAC) 2013, Austin, TX. June 2- 6, 2013.
    39. “GPU Implementation of a Scalabale, Non-Linear Congruential Generator for Cryptography Applications “, Belsare, Liu, Khatri. ACM/IEEE Great Lakes Symposium on VLSI (GLSVLSI) 2013, Paris, France. May 2-3, 2013, pp 89-94.
    40. “A Source-synchronous Htree-based Network-on-Chip “, Mandal, Khatri, Mahapatra. ACM/IEEE Great Lakes Symposium on VLSI (GLSVLSI) 2013, Paris, France. May 2-3, 2013, pp 161-166.
    41. “Architecture and 3D Device Simulation of a PIN Diode-based Gamma Radiation Detector “, Elshennawy, Marianno, Khatri. ACM/IEEE Great Lakes Symposium on VLSI (GLSVLSI) 2013, Paris, France. May 2-3, 2013, pp 329-330.
    42. “Exploring topologies for source-synchronous ring-based Network-on-Chip “, Mandal, Khatri, Mahapatra. Design Automation and Test in Europe (DATE) Conference 2013, Grenoble, France. March 18-22, 2013, pp 1026-1031.
    43. “Crosstalk avoidance codes for 3D VLSI “, Kumar, Khatri. Design Automation and Test in Europe (DATE) Conference 2013, Grenoble, France. March 18-22, 2013, pp 1673-1678.
    44. “Timing aware partitioning for multi-FPGA based logic simulation using top-down selective hierarchy flattening “, Swaminathan, Lin, Khatri. IEEE International Conference on Computer Design (ICCD) 2012, Montreal, Canada. September 30 – October 3, 2012, pp 153-158.
    45. “An efficient arithmetic Sum-of-Product (SOP) based multiplication approach for FIR filters and DFT “, Kumar, Mandal, Khatri. IEEE International Conference on Computer Design (ICCD) 2012, Montreal, Canada. September 30 – October 3, 2012, pp 195-200.
    46. “Architectural simulations of a fast, source-synchronous ring-based Network-on-Chip design “, Mandal, Khatri, Mahapatra. IEEE International Conference on Computer Design (ICCD) 2012, Montreal, Canada. September 30 – October 3, 2012, pp 482-483.”Application of Logic Synthesis to the Understanding and Cure of Genetic Diseases”. Lin, Khatri. Special session on non-traditional applications of CAD algorithms, IEEE/ACM Design Automation Conference (DAC) 2012.
    47. ”A Fast, Source-synchronous Ring-based Network-on-Chip Design”. Mandal, Khatri, Mahapatra. Design Automation and Test in Europe (DATE) conference 2012. Mar 12-26, Dresden, Germany. To appear.
    48. ”A Novel Cryptographic Key Exchange Scheme using Resistors”, Lin, Ivanov, Johnson, Khatri. IEEE International Conference on Computer Design (ICCD) 2011, Amherst, MA, Oct 2011. pp 451-452.
    49. Invited Paper, ”Noise-based Logic and Computing: What Do We Have So Far?”, Kish, Khatri, Bezrukov, Peper, Gingl, Horvath. 21st International Conference on Noise and Fluctuations. June 12-16 2011, Toronto, Canada.
    50. ”An Automated Approach for Minimum Jitter Buffered H-tree Construction”, Mandal, Jayakumar, Bollapalli, Khatri, Mahapatra. 24th International Conference on VLSI Design, Chennai, India. Jan 2-7, 2011.
    51. ”Interconnected Tile Standing Wave Resonant Oscillator based Clock Distribution Circuits”, Mandal, Karkala, Khatri, Mahapatra. 24th International Conference on VLSI Design, Chennai, India. Jan 2-7, 2011.
    52. ”Efficient Arithmetic Sum-of-Product (SOP) Based Multiple Constant Multiplication (MCM) for FFT”, Karkala, Wanstrath, Lacour, Khatri. International Conference on Computer-Aided Design (ICCAD) 2010, San Jose, CA. pp.735~738.
    53. ”Exploring a Circuit Design Approach Based on One-Hot Multi-Valued Domino Logic”, Gope, Lin, Khatri. 2010 IEEE International Midwest Symposium on Circuits & Systems (MWSCAS), Seattle, WA, Aug 1-4, 2010.
    54. ”Minimum Leakage Vector Computation Using Weighted Partial MaxSAT”, Singh, Gulati, Khatri. 2010 IEEE International Midwest Symposium on Circuits & Systems (MWSCAS), Seattle, WA, Aug 1-4, 2010.
    55. ”Unique Radiation Detection Method Using Si based Integrated Circuits”, Marianno, Khatri. 2010 Annual Meeting of the Health Physics Society, Salt Lake City, UT. Jun 27 – July1, 2010.
    56. ”An Efficient Pulse Flip-Flop Based Launch-on-Shift Scan Cell”, Kumar, Bollapalli, Khatri. IEEE International Symposium on Circuits and Systems (ISCAS) 2010, Paris, France. May 30 – Jun 2, 2010.
    57. ”VLSI Implementation of a Non-Linear Feedback Shift Register for High-Speed Cryptography Applications”, Lin, Khatri. Great Lakes Symposium on VLSI (GLS-VLSI) 2010. Providence, RI May 16-18, 2010.
    58. ”Boolean Satisfiability on a Graphics Processor”, Gulati, Khatri. Great Lakes Symposium on VLSI (GLS-VLSI) 2010. Providence, RI. May 16-18, 2010.
    59. ”A SAT-based Scheme to Determine Optimal Fix-free Codes”, Abedini, Khatri, Savari. Data Compression Conference (DCC), Snowbird, UT, Mar 24-26, 2010. Best student paper award.
    60. ”Implementing Digital Logic with Sinusoidal Supplies”, Bollapalli, Khatri, Kish. Design Automation and Test in Europe (DATE) conference, 2010, Dresden, Germany. Mar 8-12, 2010.
    61. Invited Paper ”DFM-Aware Structured ASIC Design”, Gopalani, Garg, Khatri. International Symposium on Integrated Circuits (ISIC) 2009, Singapore. December 14-16, 2009.
    62. Invited Paper ”A PTL based Highly Testable Structured ASIC Design Approach”, Gulati, Jayakumar, Khatri. International Symposium on Integrated Circuits (ISIC) 2009, Singapore. December 14-16, 2009.
    63. ”A Variation Tolerant Circuit Design Approach using Parallel Gates”, Garg, Khatri. Austin Conference on Integrated Systems and Circuits (ACISC) 2009, Austin, TX. October 26-27, 2009.
    64. ”Implementing Digital Logic with Sinusoidal Supplies”, Bollapalli, Khatri, Kish. Austin Conference on Integrated Systems and Circuits (ACISC) 2009, Austin, TX. October 26-27, 2009.
    65. ”A Weighted Partial MaxSAT Based Method to Determine the MLV for Combinational Designs”, Singh, Gulati, Khatri. Austin Conference on Integrated Systems and Circuits (ACISC) 2009, Austin, TX. October 26-27, 2009.
    66. ”On-chip Bidirectional Wiring for Heavily Pipelined Systems using Network Coding”, Bollapalli, Garg, Gulati, Khatri. IEEE International Conference on Computer Design (ICCD) 2009, Lake Tahoe, CA. October 4-7, 2009.
    67. ”A PLL Design based on a Standing Wave Resonant Oscillator”, Karkala, Bollapalli, Garg, Khatri. IEEE International Conference on Computer Design (ICCD) 2009, Lake Tahoe, CA. October 4-7, 2009.
    68. ”A Robust Pulse-triggered Flip-Flop based Enhanced Scan Cell Design”, Kumar, Bollapalli, Garg, Soni, Khatri. IEEE International Conference on Computer Design (ICCD) 2009, Lake Tahoe, CA. October 4-7, 2009.
    69. ”A Radiation Tolerant Phase Locked Loop Design for Digital Electronics”, Kumar, Karkala, Garg, Jindal, Khatri. IEEE International Conference on Computer Design (ICCD) 2009, Lake Tahoe, CA. October 4-7, 2009.
    70. ”3D Simulation and Analysis of the Radiation Tolerance of Voltage Scaled Digital Circuits”, Garg, Khatri. IEEE International Conference on Computer Design (ICCD) 2009, Lake Tahoe, CA. October 4-7, 2009.
    71. Invited Paper ”Highly Parallel Decoding of Space-Time Codes on Graphics Processing Units”, Bollapalli, Wu, Gulati, Khatri, Calderbank. Annual Allerton Conference on Communication, Control and Computing, 2009, Urbana, IL. Sept 30 – Oct 2, 2009.
    72. ”RF Receiver and Transmitter for Insect Mounted Sensor Platform”, Duperre, Burgett, Garg, Khatri. IEEE Midwest Symposium on Circuits and Systems (MWSCAS) 2009, Cancun, Mexico. August 2-5, 2009.
    73. ”An Automated Approach for SIMD Kernel Generation for GPU based Software Acceleration”, Gulati, Khatri. Symposium on Application Accelerators in High Performance Computing (SAAHPC) 2009, Urbana, IL. July 28-30, 2009.
    74. ”Sorting Binary Numbers in Hardware – a Novel Algorithm and its Implementation”, Alaparthi, Gulati, Khatri. International Symposium on Circuits and Systems (ISCAS) 2009, Taipei, Taiwan. May 24-27, 2009.
    75. ”Low Power and High Performance SRAM Design using Selective Forward Body Bias”, Bollapalli, Garg, Gulati, Khatri. IEEE/ACM Great Lakes Symposium on VLSI (GLSVLSI) 2009, Boston, MA. May 10-12, 2009.
    76. ”Robust Window-based Multi-node Technology-Independent Logic Minimization”, Cobb, Gulati, Khatri. IEEE/ACM Great Lakes Symposium on VLSI (GLSVLSI) 2009, Boston, MA. May 10-12, 2009.
    77. ”SEU Hardened Clock Regeneration Circuits”, Dash, Garg, Khatri, Choi. International Symposium on Quality Electronic Design (ISQED) San Jose, CA. Mar 16-18 2009.
    78. ”Design and Implementation of a Sub-threshold BFSK Transmitter”, Paul, Garg, Khatri, Vaidya. International Symposium on Quality Electronic Design (ISQED) San Jose, CA. Mar 16-18 2009.
    79. ”Closed-Loop Modeling of Power and Temperature Profiles of FPGAs”, Gulati, Khatri, Li. ACM/SIGDA International Symposium on Field Programmable Gate Arrays (FPGA). Monterey, CA. Feb 22-24 2009, pp. 287.
    80. ”Accelerating Statistical Static Timing Analysis Using Graphics Processing Units”, Gulati, Khatri. IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC) 2009, Yokohama, Japan, Jan 19-22 2009, pp. 260-265.
    81. ”Efficient Analytical Determination of the SEU-induced Pulse Shape”, Garg, Khatri. IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC) 2009, Yokohama, Japan, Jan 19-22 2009, pp. 461-467. Selected among the finalists for the best paper award at the conference.
    82. ”Fast Circuit Simulation on Graphics Processing Units”, Gulati, Croix, Khatri, Shastry. IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC) 2009, Yokohama, Japan, Jan 19-22 2009, pp. 403-408.
    83. ”A Novel, Highly SEU Tolerant Digital Circuit Design Approach”, Garg, Khatri. IEEE International Conference on Computer Design (ICCD) 2008, Lake Tahoe, CA, October 12-15 2008, pp. 14-20.
    84. ”A Timing-Driven Synthesis Approach of a Fast Four-Stage Hybrid Adder in Sum-of-Products”, Das, Khatri. IEEE Midwest Symposium on Circuits and Systems (MWSCAS) 2008, August 10-13, 2008, Knoxville, TN, pp. 507-510.
    85. ”Forbidden Transition Free Crosstalk Avoidance CODEC Design”, Duan, Khatri. ACM/EDAC/IEEE Design Automation Conference (DAC) 2008, June 8-13 2008, Anaheim, CA, pp. 986-991.
    86. ”Towards Acceleration of Fault Simulation using Graphics Processing Units”, Gulati, Khatri. ACM/ EDAC/IEEE Design Automation Conference (DAC) 2008, June 8-13 2008, Anaheim, CA, pp. 822-827.
    87. ”A Fast, Analytical Estimator for the SEU-induced Pulse Width in Combinational Designs”, Garg, Nagpal, Khatri. ACM/ EDAC/IEEE Design Automation Conference (DAC) 2008, June 8-13 2008, Anaheim, CA, pp. 918-923.
    88. ”Modeling Dynamic Stability of SRAMs in the Presence of Single Event Upsets (SEUs)”, Garg, Li, Khatri. IEEE International Symposium on Circuits and Systems, 18-21 May 2008, Seattle, WA, pp. 1788-1791.
    89. ”Accelerating Statistical Static Timing Analysis Using Graphics Processing Units”, Gulati, Khatri. Austin Conference on Integrated Systems and Circuits (ACISC) 2008, May 7-9, Austin, TX.
    90. ”A Lithography-friendly Structured ASIC Design Approach”, Gopalani, Garg, Khatri, Cheng. IEEE Great Lakes Symposium on VLSI, May 4-6, 2008, Orlando, FL, pp. 315-320.
    91. ”Pipelined Network of PLA Based Circuit Design”, Paul, Garg, Khatri. IEEE Great Lakes Symposium on VLSI, May 4-6, 2008, Orlando, FL, pp. 213-218.
    92. ”A Robust, Fast Pulsed Flip-Flop Design”, Venkatraman, Garg, Khatri. IEEE Great Lakes Symposium on VLSI, May 4-6, 2008, Orlando, FL, pp. 119-122.
    93. ”Improving FPGA routability using network coding”, Gulati, Khatri. IEEE Great Lakes Symposium on VLSI, May 4-6, 2008, Orlando, FL, pp. 147-150.
    94. ”A Delay-Efficient Radiation-Hard Digital Design Approach Using CWSP Elements”, Nagpal, Garg, Khatri. Design Automation, and Test in Europe (DATE) Conference 2008, 10-14 March, Munich, Germany, pp. 354-359.
    95. ”Energy Efficient and High Speed On-Chip Ternary Bus”, Duan, Khatri. Design Automation, and Test in Europe (DATE) Conference 2008, 10-14 March, Munich, Germany, pp. 515-518.
    96. ”A Single-Supply True Voltage Level Shifter”, Garg, Mallarapu, Khatri. Design Automation, and Test in Europe (DATE) Conference 2008, 10-14 March, Munich, Germany, pp. 979-984.
    97. ”Clock distribution scheme using coplanar transmission lines”, Cordero, Khatri. Design Automation, and Test in Europe (DATE) Conference 2008, 10-14 March, Munich, Germany, pp. 985-990.
    98. ”A Merged Synthesis Technique for Fast Arithmetic Blocks Involving Sum-of-Products and Shifters”, Das, Khatri. 21st International Conference on VLSI Design 2008, January 4-8, Hyderabad, India, pp. 572-579.
    99. ”A Timing-Driven Synthesis Technique for Arithmetic Product-of-Sum Expressions”, Das, Khatri. 21st International Conference on VLSI Design 2008, January 4-8, Hyderabad, India, pp. 635-640.
    100. ”An Inversion-Based Synthesis Approach for Area and Power Efficient Arithmetic Sum-of-Products”, Das, Khatri. 21st International Conference on VLSI Design 2008, January 4-8, Hyderabad, India, pp. 653-659.
    101. Invited Paper ”Extreme Low Power Computing using Sub-threshold Circuits”, Segundo Magno Congreso Interancional del CIC 2007, Mexico City, Mexico, November 6-8, 2007.
    102. ”VLSI Implementation of a Staggered Sphere Decoder Design for MIMO Detection”, Bhagawat, Ekambavanan, Das, Choi, Khatri. 45th Annual Allerton Conference on Communication, Control and Computing, Sept 26-28, 2007, Urbana, IL, pp. 228-235.
    103. ”Toggle Equivalence Preserving (TEP) Logic Optimization”, Goldberg, Gulati, Khatri. 10th Euromicro Conference on Digital System Design (Architectures, Methods and Tools), Aug 29-31, 2007, Lubeck, Germany, pp. 271-279.
    104. ”A Generic Radar Processor Design Using Software Defined Radio”, Brimeyer, Martin, Loew, Farquharson, Khatri, Paul. 33rd American Meteorology Society (AMS) Conference on Radar Meteorology, Aug 6-10, 2007, Cairns, Australia.
    105. ”Timing-Driven Decomposition of a Fast Barrel Shifter”, Das, Khatri. IEEE International Midwest Symposium on Circuits and Systems (MWCAS) 2007, August 5-8, Montreal, Canada, pp. 574-577.
    106. ”FPGA Based Signal Processing Platform For Weather Radar”, Paul, Khatri, Martin, Brimeyer, Loew, Vivekanandan. International Geoscience and Remote Sensing Symposium (IGARSS) 2007, July 23-27, Barcelona, Spain.
    107. ”Area-reducing Sharing of Mutually Exclusive Multiplier, MAC, Adder and Subtractor blocks”, Das, Khatri. IASTED Fifth International Conference on Circuits, Signals and Systems (CSS) 2007, July 2-4, Banff, Alberta.
    108. ”A Timing-Driven Hybrid-Compression Algorithm for Faster Sum-of-Products”, Das, Khatri. IASTED Fifth International Conference on Circuits, Signals and Systems (CSS) 2007, July 2-4, Banff, Alberta.
    109. ”Generation of the Optimal Bit-Width Topology of the Fast Hybrid Adder in a Parallel Multiplier”, Das, Khatri. International Conference on Integrated Circuit Design and Technology (ICICDT) 2007, May 30 – June 1, Austin, TX, pp. 1-6.
    110. ”A Structured ASIC Design Approach Using Pass Transistor Logic”, Gulati, Jayakumar, Khatri. IEEE International Symposium on Circuits and Systems (ISCAS) 2007, May 27-30, New Orleans, LA, pp. 1787-1790.
    111. ”An Algorithm to Minimize Leakage through Simultaneous Input Vector Control and Circuit Modification”, Jayakumar, Khatri. Design Automation and Test in Europe (DATE) Conference 2007, April 16-20, Nice, France, pp. 618-623.
    112. ”A Methodology for Interconnect Dimension Determination”, Cobb, Garg, Khatri. ACM International Symposium on Physical Design (ISPD) 2007, Mar 18-21, Austin, TX, pp. 189-195.
    113. ”Network Coding for Routability Improvement in VLSI”, Jayakumar, Gulati, Khatri, Sprintson. IEEE International Conference on Computer-Aided Design (ICCAD), Nov 5-9, 2006, San Jose, CA, pp. 820-823.
    114. ”On the Improvement of Statistical Static Timing Analysis”, Garg, Jayakumar, Khatri. IEEE International Conference on Computer Design (ICCD), Oct 1-4, 2006, San Jose, CA, pp. 37-42.
    115. ”An Efficient, Scalable Hardware Engine for Boolean Satisfiability”, Waghmode, Gulati, Khatri, Shi. IEEE International Conference on Computer Design (ICCD), Oct 1-4, 2006, San Jose, CA, pp. 326-331.
    116. ”CMOS Comparators for High-Speed and Low-Power Applications”, Menendez, Maduike, Garg, Khatri. IEEE International Conference on Computer Design (ICCD), Oct 1-4, 2006, San Jose, CA, pp. 76-81.
    117. ”A Design Approach for Radiation-hard Digital Electronics”, Garg, Jayakumar, Khatri. ACM/IEEE Design Automation Conference (DAC), July 24-28 2006, pp. 773-778.
    118. ”A PLA based Asynchronous Micropipelining Approach for Subthreshold Circuit Design”, Jayakumar, Garg, Gamache, Khatri. ACM/IEEE Design Automation Conference (DAC), July 24-28 2006, pp. 419-424.
    119. ”Generalized Buffering of PTL Logic Stages using Boolean Division”, Garg, Khatri. IEEE International Symposium on Circuits and Systems (ISCAS), May 21-24 2006, Kos, Greece, pp. 5615-5618.
    120. ”Efficient Don’t Care Computation for Hierarchical Designs”, Gulati, Lovell, Khatri. IEEE International Symposium on Circuits and Systems (ISCAS), May 21-24 2006, Kos, Greece, pp. 3037-3040.
    121. ”Computing During Supply Voltage Switching in DVS Enabled Real-time Processors”, Duan, Khatri. IEEE International Symposium on Circuits and Systems (ISCAS), May 21-24 2006, Kos, Greece, pp. 5115-5118.
    122. ”A Probabilistic Method to Determine the Minimum Leakage Vector for Combinational Designs”, Gulati, Jayakumar, Khatri. IEEE International Symposium on Circuits and Systems (ISCAS), May 21-24 2006, Kos, Greece, pp. 2241-2244.
    123. ”Memory-based Cross-talk Canceling CODECs for On-chip Buses”, Duan, Gulati, Khatri. IEEE International Symposium on Circuits and Systems (ISCAS), May 21-24 2006, Kos, Greece, pp. 1119-1122.
    124. ”A High-speed Fully Programmable VLSI Decoder for Regular Low Density Parity Check (LDPC) Codes”, Kim, Jayakumar, Bhagwat, Selvarathinam, Choi, Khatri. IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP) 2006, May 14-19, Toulouse, France, pp. III:972-III:975.
    125. ”Implementation of MOSFET based Capacitors for Digital Applications”, Shen, Khatri, Zourntos. IEEE/ACM Great Lakes Symposium on VLSI (GLSVLSI), April 30 – May 2, 2006, Philadelphia, PA, pp. 180-185.
    126. ”Resource and Delay Efficient Matrix Multiplication using Newer FPGA Devices”, Campbell, Khatri. IEEE/ACM Great Lakes Symposium on VLSI (GLSVLSI), April 30 – May 2, 2006, Philadelphia, PA, pp. 308-311.
    127. ”A Design Flow to Optimize Circuit Delay by Using Standard Cells and PLAs”, Garg, Sanchez, Gulati, Jayakumar, Gupta, Khatri. IEEE/ACM Great Lakes Symposium on VLSI (GLSVLSI), April 30 – May 2, 2006, Philadelphia, PA, pp. 217-222.
    128. ”Bus Stuttering : An Encoding Technique to Reduce Inductive Noise in Off-Chip Data Transmission”, LaMeres, Khatri. Design Automation and Test in Europe (DATE) conference, March 6-10 2006, Munich, Germany, pp. 522-527.
    129. ”Impedance Matching Techniques for VLSI Packaging”, LaMeres, Garg, Gulati, Khatri. DesignCon 2006, February 6-9, 2006, Santa Clara, CA.
    130. ”Controlling Inductive Cross-talk and Power in Off-chip Buses using CODECs”, LaMeres, Gulati, Khatri. Asia Pacific Design Automation Conference (ASPDAC) 2006, January 24-27, Yokohama, Japan, pp. 850-855.
    131. ”Efficient SAT-based Combinational ATPG using Multi-level Don’t-Cares”, Saluja, Khatri. International Test Conference (ITC) 2005, Nov 8-10, Austin, TX, pp. 1038-1047.
    132. ”Practical Techniques to Reduce Skew and its Variations in Buffered Clock Networks”, Venkataraman, Jayakumar, Hu, Li, Khatri, Rajaram, McGuinness, Alpert. International Conference on Computer-Aided Design (ICCAD) 2005, Nov 6-10, San Jose, CA, pp. 592-596.
    133. ”X-Routing using Two Manhattan Route Instances”, Ahmad, Jayakumar, Balasubramanian, Hursey, Khatri, Mahapatra. International Conference on Computer Design (ICCD) 2005, Oct 2-5, San Jose, CA, pp. 45-50.
    134. ”Minimum Energy Near-threshold Network of PLA based Design”, Jayakumar, Khatri. International Conference on Computer Design (ICCD) 2005, Oct 2-5, San Jose, CA, pp. 399-404.
    135. ”Broadband Impedance Matching for Inductive Interconnect in VLSI Packages”, LaMeres, Khatri. International Conference on Computer Design (ICCD) 2005, Oct 2-5, San Jose, CA, pp. 683-688. Best Paper Award, ICCD 2005
    136. ”Design of a Low-Power Differential Repeater Using Low-Voltage Swing and Charge Recycling”, LaMeres, Khatri. DesignCon East 2005, Sept 19-21, Worcester, MA.
    137. ”Performance Model for Inter-Chip Busses Considering Bandwidth and Cost” LaMeres, Khatri. DesignCon East, Sept 19-21, Worcester, MA. Best Paper Award, DesignCon 2005.
    138. ”An Algebraic Decision Diagram (ADD) Based Technique to find Leakage Histograms of Combinational Designs”, Gulati, Jayakumar, Khatri. International Symposium on Low Power Electronic Design (ISLPED) 2005, August 8-10, San Diego, CA, pp. 111-114.
    139. ”A Self-adjusting Scheme to Determine the Optimum RBB by Monitoring Leakage Currents”, Jayakumar, Dhar, Khatri. Design Automation Conference (DAC) 2005, Anaheim, CA, June 13-17, pp. 43-46.
    140. ”A Variation-tolerant Sub-threshold Design Approach”, Jayakumar, Khatri. Design Automation Conference (DAC), 2005 Anaheim, CA , June 13-17, pp. 716-719.
    141. ”Performance Model for Inter-chip Communication Considering Inductive Cross-talk and Cost”, LaMeres, Khatri. IEEE International Symposium on Circuits and Systems, Kobe, Japan, May 23 – 26 2005, pp. 4130-4133.
    142. ”A Boolean Satisfiability based Solution to the Routing and Wavelength Assignment Problem in Optical Telecommunication Networks”, Valavi, Saluja, Khatri. International Conference on Communications (ICC), May 16 – 20 2005, Seoul, pp. 1802-1806.
    143. ”Encoding-based Minimization of Inductive Cross-talk for Off-chip Data Transmission”, LaMeres, Khatri. Design Automation and Test in Europe (DATE) conference, March 2005, pp. 1318-1323.
    144. ”A Dynamic Voltage Scaling Algorithm for Energy Reduction in Hard Real-Time Systems”, Culver, Khatri. Asia South Pacific Design Automation Conference (ASP-DAC) 05, January 2005, pp. 842-845.
    145. ”Non-Manhattan Routing using a Manhattan Router”, Hursey, Jayakumar, Khatri. VLSI Design 05, pp. 445-450. Selected among the top 4 papers at the conference, and was a best paper nominee.
    146. ”Design of a Low-power Differential Repeater using Low Voltage Swing and Charge Recycling”, LaMeres, Khatri. DesignCon-05, Jan 2005.
    147. ”Performance Model for Inter-chip Busses Considering Bandwidth and Cost”, LaMeres, Khatri. DesignCon-05, January 2005. Selected among the finalists for the best paper award at the conference.
    148. ”A Novel Clock Distribution and Dynamic De-skewing Methodology”, Kapoor, Jayakumar, Khatri. International Conference on Computer-Aided Design (ICCAD), Nov 2004, pp. 626-631.
    149. ”A METAL and VIA Maskset Programmable VLSI Design Methodology using PLAs”, Jayakumar, Khatri. International Conference on Computer-Aided Design (ICCAD), Nov 2004, pp. 590-594.
    150. ”High Throughput VLSI Implementations of Iterative Decoders and Related Code Construction Problems”, Nagarajan, Jayakumar, Khatri, Milenkovic. GlobeComm 2004, pp. 361-365.
    151. ”A Robust Algorithm For Approximate Compatible Observability Don’t Care (CODC) Computation”, Saluja, Khatri. Design Automation Conference (DAC), June 2004, pp. 422-427.
    152. ”Exploiting Crosstalk to Speed up On-chip Buses”, Duan, Khatri. Design Automation and Test in Europe (DATE) conference, February 2004, pp. 778-783.
    153. ”A Differential Amplifier Based Technique to Reduce Delay in Long Interconnect”, Purandare, Sung, Khatri. International Conference on VLSI Design, January 2004.
    154. ”An ASIC Design Methodology with Predictably Low Leakage, using Leakage-immune Standard Cells”, Jayakumar, Khatri. International Symposium on Low Power Electronics and Design (ISLPED-03), Seoul, Korea, Aug 2003, pp. 128-133.
    155. ”IP Routing Table Compression Using ESPRESSO-MV”, Bian, Khatri. 11th International Conference on Networking (ICON-03), Sydney, Australia, September 2003, pp. 167-172.
    156. ”A Fast Ternary CAM Design for IP Networking Applications”, Gamache, Pfeffer, Khatri. 12th International Conference on Computer Communications and Networks (IC3N-03), Dallas, TX, October 2003, pp. 434-439. Selected among the finalists for the best paper award at the conference.
    157. ”Addressing The Timing Closure Problem By Integrating Logic Optimization And Placement,” Gosti, Khatri, Sangiovanni-Vincentelli. IEEE/ACM International Conference on Computer-Aided Design (ICCAD-2001). Nov 2001, Santa Clara, CA, pp. 224-231.
    158. ”Analysis and Avoidance of Cross-talk in On-Chip Buses”, Duan, Tirumala, Khatri. Published at IEEE Symposium on High-Performance Interconnects (HOT Interconnects 2001), August 22-24, 2001, pp 133-138, Stanford, CA, pp. 133-138.
    159. ”A Regularity-driven Fast Gridless Detailed Router for High Frequency Datapath Designs”, Das, Khatri. Presented at International Symposium on Physical Design (ISPD-01), April 1-4, 2001, pp 130-135, Sonoma, CA, pp. 130-135.
    160. ”Cross-talk Immune VLSI Design using a Network of PLAs Embedded in a Regular Layout Fabric”- Khatri, Brayton, Sangiovanni-Vincentelli. IEEE/ACM International Conference on Computer-Aided Design (ICCAD-2000), Nov 2000, pp 412-418, Santa Clara, CA, 412-419.
    161. ”Binary and Multi-Valued SPFD-based Wire Removal in PLA Networks”- Khatri, Sinha, Brayton, Sangiovanni-Vincentelli. International Conference on Computer Design (ICCD-2000), pp 494-503, Austin, TX, pp. 494-503.
    162. ”A Novel VLSI Layout Fabric for Deep Sub-Micron Applications”- Khatri, Mehrotra, Brayton, Sangiovanni-Vincentelli, Otten. 36th Design Automation Conference (DAC-99), pp 491-496, New Orleans, LA, pp. 491-496.
    163. Invited paper ”Multi-valued Logic Synthesis”- Brayton, Khatri. 12th International Conference on VLSI Design (VLSI-99), pp 196-205, Goa, India, pp. 196-205.
    164. ”Sequential Multi-valued Network Simplification using Redundancy Removal” – Khatri, Brayton, Sangiovanni-Vincentelli. 12th International Conference on VLSI Design, (VLSI-99) , pp 206-211, Goa, India.
    165. ”A Timed Automaton-based Method for Accurate Circuit Delay Computation in the Presence of Cross-talk”- Tasiran, Khatri, Yovine, Brayton, Sangiovanni-Vincentelli. International Conference on Formal Methods in Computer-Aided Design, Palo Alto, CA, Nov 1998, pp. 149-166.
    166. ”VIS” – Brayton, Hachtel, Sangiovanni-Vincentelli, Somenzi, Aziz, Cheng, Edwards, Khatri, Kukimoto, Pardo, Qadeer, Ranjan, Sarwary, Shiple, Swamy, Villa. International Conference on Formal Methods in Computer-Aided Design, Palo Alto, CA, Nov 1996, pp 428-432.
    167. ”Decomposition Techniques for Efficient ROBDD Construction” – Jain, Narayan, Coelho, Khatri, Sangiovanni-Vincentelli, Brayton, Fujita. International Conference on Formal Methods in Computer-Aided Design, pp 248-256, Palo Alto, CA, Nov 1996.
    168. ”Engineering Change in a Non-Deterministic FSM Setting” – Khatri, Narayan, Krishnan, McMillan, Sangiovanni-Vincentelli, Brayton. Presented at the 33rd Design Automation Conference, Las Vegas, NV, June 1996, pp 451-456.
    169. ”A Study of Composition Schemes for Mixed Apply/Compose Based Construction of ROBDDs” – Narayan, Khatri, Jain, Fujita, Brayton, Sangiovanni-Vincentelli. Presented at the Ninth International Conference on VLSI Design, Bangalore, India, Jan 1996, pp 249-253.
    170. ”VIS: A System for Verification and Synthesis” – Brayton, Hachtel, Sangiovanni-Vincentelli, Somenzi, Aziz, Cheng, Edwards, Khatri, Kukimoto, Pardo, Qadeer, Ranjan, Sarwary, Shiple, Swamy, Villa. Presented at the 8th International Computer-Aided Verification Conference, New Brunswick, NJ, Jul-Aug 1996, pp 428-432.

• • 1. ”Efficient Cancer Therapy using Boolean Networks and Max-SAT-based ATPG”, Lin, Khatri. 2010 IEEE International Workshop on Genomic Signal Processing and Statistics (GENSIPS). Dec 2011, San Antonio, TX.
    2. “A Comparison of Low Standby Power Techniques for an Asynchronous NoC Router”, Fairouz, Khatri. 2017 IEEE Texas Workshop on Integrated System Exploration (TexasWISE). Dallas, TX, April 2017.
    3. “Design of a Hardware Hash Unit for use in Modern Microprocessors”, Fairouz, Khatri. 2017. IEEE Texas Workshop on Integrated System Exploration (TexasWISE). Dallas, TX, April 2017.
    4. ” A Practical Methodology to Validate the Statistical Behavior of Bloom Filters”, Kottapalli, Khatri. IEEE Texas Workshop on Integrated System Exploration (TexasWISE) 2016, Houston, TX, May 2016
    5. ” Accelerating Bayesian Control of Markovian Genetic Regulatory Networks on a GPU”, Zhou, Hu, Khatri, Liu, Sze, Yousefi. IEEE Texas Workshop on Integrated System Exploration (TexasWISE) 2016, Houston, TX, May 2016.
    6. ” Ternary-valued Digital Circuit Implementation using Flash Transistors”, Abusultan, Khatri, Datta. IEEE Texas Workshop on Integrated System Exploration (TexasWISE) 2016, Houston, TX, May 2016.
    7. ” A CPU-GPU Heterogeneous Algorithm for NGS Read Alignment”, Al Kawam, Khatri, Datta. IEEE Texas Workshop on Integrated System Exploration (TexasWISE) 2016, Houston, TX, May 2016.
    8. ” Design of a Robust C-Element for Asynchronous Circuit Design”, Sharma, Khatri. IEEE Texas Workshop on Integrated System Exploration (TexasWISE) 2016, Houston, TX, May 2016.
    9. “ An Increase in Optical Photon Collection Efficiency of a Sodium Iodide Crystal,” Shah, Marianno, Khatri. Health Physics Society 60th Annual Meeting, Indianapolis, IN, 2015.
    10. Invited paper,  “Information, noise and energy dissipation: Laws, limits and applications”, Kish, Granqvist, Khatri, Sundqvist, Peper Plenary talk at International Workshop on Molecular Architectonics, Shiretoko, Hokkaido, Japan, August 3-6, 2015.
    11. ” Radiation Detection Using Integrated Circuits”,  Shah, Marianno, Khatri. Accepted at the 59th Annual Meeting of the Health Physics Society, Baltimore, MD. 2014.
    12. “ An FPGA LUT Design to Explore the Power and Speed Tradeoff”, Abusultan, Khatri. Accepted at the 2014 IEEE Texas Workshop on Integrated System Exploration (TexasWISE), Austin, TX. March 21, 2014.
    13. “ Correcting for Multiple Detections of the Same Event in a Multi-Sensor Environment”, Bass, Abusultan, Elshennawy, Khatri. Accepted at the 2014 IEEE Texas Workshop on Integrated System Exploration (TexasWISE), Austin, TX. March 21, 2014.
    14. ” Gene Predictor Ranking and Function Selection Using Zhegalkin Functions”, Lin, Khatri. The First Workshop on Modeling of Biological Systems (MoBS) 2013, Austin, TX. June 2013.
    15. ” A Technique for Fast Data Transfer using Sinusoidal Signals”, Mandal, Khatri, Entesari, Gharpurey, Abrahams, Mahapatra. IEEE Texas Workshop on Integrated System Exploration (TXWISE) 2013, Winedale, TX. March 2013.
    16. ” Determining gene function in Boolean networks using Boolean Satisfiability”, Lin, Khatri. IEEE International Workshop on Genomic Signal Processing and Statistics (GENSiPS) 2012, Washington, DC. December 2-4, 2012, pp 176-179.
    17. ” Efficient Solid State Gamma Radiation Detector,” Elshennawy, Marianno, Khatri. Symposium on Radiation Measurements and Applications (SORMA) 2012, Berkeley, CA. May 14-17, 2012.
    18. ”Inference of Gene Predictor Set using Boolean Satisfiability”, Lin, Khatri. 2010 IEEE International Workshop on Genomic Signal Processing and Statistics (GENSIPS). Nov 2010, Cold Spring Harbor, NY. pp 1-4.
    19. ”Fault Dictionary Computation using Graphics Processing Units”, Gulati, Khatri. IEEE International High Level Design Validation and Test Workshop (HLDVT) 2009, San Francisco, CA. November 4-6, 2009.
    20. Invited Paper ”Noise-based logic and computing: from Boolean logic gates to brain circuitry and its possible hardware realization”, Kish, Bezrukov, Khatri, Gingl, Sethuraman. International W

My courses at Texas A&M are listed below: 

EE 248 – Introduction to Computer Systems Design. This course covers fundamental concepts in computer systems design such as binary arithmetic, Boolean functions and their representation, two-level and multi-level logic, and finite state machines

EE 289/689 – Career Tips for ECE Students. The course focuses on designing a long and rewarding career. It covers several tips such as how one can write an effective CV, how one can perform well at in-person and online interviews with mock interviews, managing AI in your career, techniques for effective networking, approaches for continuous evaluation and monitoring of one’s career trajectory, approaches for being effective at the job, and time management and work-life balance. Guest lectures from industry will be invited to present their opinions on career management

EE 449/749 – Microprocessor System Design. This lab course covers several embedded design techniques. The lab material is based on a Xilinx XUP2VP30 board, which has reconfigurable logic as well as a pair of PowerPC 405 microprocessors on the same integrated circuit. The labs cover hardware and software codesign exercises.

EE489/689 – Introduction to Chiplet Design. This lab focuses on design of chiplet-based VLSI systems. It includes technology and design implications of organizing VLSI systems into chiplets. It also addresses issues in fabricating and testing chiplet systems. Design tasks and electronic design automation tools for those tasks will be presented.

EE 454 – Digital Integrated Circuit Design. This course covers several digital IC design techniques. We start with MOSFET modeling, then cover static and dynamic characteristics of typical digital circuits. We will discuss IC design techniques as applicable in industrial practice.

EE 689 – Scalable Distributed Consensus. This course will cover advanced topics in distributed consensus, which is the core algorithm used in several blockchain based

applications. Particular emphasis will be given to scalablility.

EE 689 – Quantum and Logic Synthesis. This covers both classical logic synthesis (methods for efficient representation and optimization of logic) and quantum logic synthesis, and the “bridge” between them.

EE 699 – VLSI Logic Synthesis. This course covers different methods for logic representation, manipulation, and optimization, for both combinational and sequential logic. The course views logic synthesis in the context of the implementation styles that are popularly used in industry today.

EE 752 – Advances in VLSI Circuit Design. The class covers design techniques applicable in a custom VLSI design setting. We cover various CMOS circuit design styles, design and simulation techniques including 3-D parasitic extraction, leakage power reduction and exploitation, dynamic compensation of circuit behavior, design of semiconductor memories, packaging issues and transmission line analysis.

Below is a list of the graduate and undergraduate courses that I taught at the University of Colorado, Boulder. My graduate classes are research-centric, and usually have a research project in lieu of a final exam. 

ECEN 6013 – Computer-Aided Design Techniques for VLSI

This class covers circuit-level, switch-level, and logic-level simulation techniques in addition to physical design topics like circuit partitioning, placement and global as well as detailed routing. This course was first offered in the Fall 2002 semester.

ECEN 6003 – Digital Circuit Design 

The class covers design techniques applicable in a custom VLSI design setting. We cover various CMOS circuit design styles, design and simulation techniques including 3-D parasitic extraction, design of semiconductor memories, packaging issues and transmission line analysis.

ECEN 6139 – VLSI Logic Synthesis

This course deals with logic synthesis techniques for VLSI, with an emphasis on the VLSI design techniques that drive corresponding logic synthesis algorithms. We cover two-level logic optimization, multi-valued logic optimization, multi-level network optimization, multi-level don’t cares, factorization, timing optimization, technology mapping, testing, Sets of Pairs of Functions to be Distinguished (SPFDs), sequential circuit optimization

ECEN 6009 – Research Topics in VLSI

This is a research-oriented course which includes readings in the areas of Embedded Systems (scheduling, power considerations, new hardware paradigms etc.), Nano-electronics and Quantum Computing.

My undergraduate classes at the University of Colorado, Boulder, have been in the area of switching theory. 

ECEN 4703 – Switching and Finite Automata Theory 

This is an undergraduate course on fundamentals of switching theory, two-level and multi-level logic optimization and finite automata theory.

Current Students :

Kent Lin

is working on his PhD with my group since Spring 2009, in the areas of GPU based extraction of the Gene Regulatory Network for cancer, as well as in the design of special function units to accelerate computing, and on cryptographic key generator circuits. Kent received his BS degree from UC Berkeley, and his MS degree from Yale University.

Ayan Mandal

is working on his PhD with my group since Spring 2010, in the areas of resonant clock based source-synchronous Network on Chip (NoC) design, special purpose functional units for hash and sort operations, and on low-jitter clock distribution networks. Ayan received his BS degree from IIT Kharagpur, India. Ayan is co-advised by Prof. Rabi Mahapatra (CS, TAMU).

Monther Abusultan

is working towards his PhD degree since Fall 2010. His research consists of FPGA circuits that can explore the power-delay tradeoff by operating from sub-threshold through full supply operation. Monther has his BS and MS degrees from Montana State University, Bozeman, MT.

Amr Elshennawy

started on his PhD degree in Fall 2011. His research interests include GPU based implementations of algorithms (Boolean Satisfiability, radiation transport), and radiation detection circuits. Amr obtained his BS from Cairo University in Egypt in 2009, and worked as a software engineer (at IBM, Mentor Graphics and Cerner Corp.) between 2009 and 2011.

Suraj Prakash

is working on his PhD degree since Spring 2012. His research is in the design of fast special function units using memristor devices. Suraj obtained his BS from IIT Roorkee in India in 2007, and worked at ST Microelectronics from 2007 to 2011.

Subramanian Poothamkurissi

is working on his MS degree since Fall 2010. His research consists of partitioning RTL netlists for FPGA based emulation. Subramanian has his BS degree from NIT Trichy in India.

Rajeev Kumar

is working on his MS degree since Spring 2011. His research is on fast FFT computations using Sum-of-Product (SOP) based architectures. Rajeev has his undergraduate degree from IIT Guwahati in India, in 2007. Rajeev worked at ARM from 2007 to 2010.

Darshit Mehta

has been working on his MS degree since Fall 2011. His research is on resilient clock networks. Darshit obtained his BS in EE from BITS Pilani in India, in 2011.

Past Students :

Kanupriya Gulati

obtained her PhD degree in Fall 2009. Kanu’s PhD dissertation was on the use of Graphics Processing Units (GPUs) for EDA. In addition, Kanu worked on logic synthesis techniques for leakage computation, hierarchical don’t care computation and BDD-based synthesis of structured ASICs. Kanupriya has a B.S. from the Delhi College of Engineering, India, and an M.S. degree in ECE from Texas A&M University (from my group). Kanu’s M.S. thesis was on efficient means to compute circuit leakage histograms and to compute the input vector that minimizes leakage for combinational circuits. Kanu is currently with Intel Corporation in Hillsboro, OR.

Rajesh Garg

defended his Ph.D. in Spring 2009. Rajesh’s Ph.D. work was on radiation-tolerant circuit design and pass transistor logic. Rajesh obtained his B.S. from the Indian Institute of Technology, Delhi, India. Rajesh obtained his M.S. in ECE from Texas A&M University in Spring 2006 (from my group). His M.S. thesis was on generalized buffering in pass transistor structures, using Boolean division and Approximate Compatible Observability Don’t Cares (ACODCs). Rajesh is currently with Intel Corporation in Hillsboro, OR.

Chunjie Duan

received his Ph.D. in 2008. His dissertation was on capacitive cross-talk alleviation in on-chip buses using specialized CODECs. Chunjie has a M.S. from Colorado State University and a B.S. from Tsinghua University in China. Chunjie works at the Mitsubishi Electric Research Laboratories (MERL) in Boston, MA.

Sabyasachi Das

obtained his Ph.D. candidate in Fall 2007, working on design automation techniques for datapath circuit design, including datapath synthesis and routing. Sabya’s work included datapath synthesis tools for area-critical as well as timing-critical datapath components such as adders, Sum-of-Product (SOP) blocks, shifters. Sabya has a B.S. from Jadavpur University, India, and an M.S. degree in ECE from the University of Massachusetts, Amherst. Sabya is currently with Xilinx Inc, in Santa Clara, CA.

Nikhil Jayakumar

obtained his Ph.D. in 2006. His PhD dissertation work was on the minimization and exploitation of leakage in contemporary VLSI design. This work included leakage minimization by using a novel low-leakage standard cell approach, and a methodology to minimize total leakage via optimal reverse body bias. Also, it included approaches to exploit leakage using subthreshold circuit design, and means to minimize energy and maximize performance via micro-pipelining in this framework. Nikhil is currently with Juniper Networks in San Jose, CA.

Brock LaMeres

obtained his Ph.D. in 2005. Brock’s dissertation work was on high-speed board-level design (performance model of off-chip buses including inductive cross-talk effects, controlling inductive cross-talk in off-chip buses using CODECs, and static/dynamic techniques to adjust package inductance to match the board). Brock is currently with Montana State University in Bozeman, MT.

Rajesh Kumar

obtained his MS degree in Summer 2010. Rajesh’s thesis work involved radiation tolerant VLSI design. Rajesh obtained his B.S. from IIT Roorkee, and has 2 years experience with ST Microelectronics.

Vinay Karkala

obtained his MS degree in Summer 2010. Vinay’s was on resonant clocking for VLSI design. Vinay obtained his B.S. from IIT Madras, India, and has 1 years experience with Cypress Semiconductor.

Kalyana Bollapalli

obtained his MS degree in Fall 2009. Kalyana’s MS work included techniques to perform fast IP routing table lookup using Logic Minimization techniques. In addition, Kalyana worked on GPU based MIMO decoding, noise based logic, low-leakage SRAM design and unicast network coding for on-chip wiring improvement. Kalyan obtained his B.S. from IIT Bombay, and has 3 years experience with Infineon Technologies. Kalyana is currently with NVIDIA Corporation in San Jose, CA.

Charu Nagpal

obtained her M.S. degree in Spring 2008. Charu’s thesis was on developing techniques to perform radiation tolerant circuit design. Charu has a B.S. in EE from the Netaji Subhas Institue of Technology in Delhi, India. Charu is currently with Intel Corporation in Austin, TX.

Suganth Paul

obtained his M.S. degree in Fall 2007. Suganth’s work included techniques to perform fast computer arithmetic, approximate computation of the logarithm function in hardware, and a sub-threshold BFSK transmitter chip, implemented in a 0.25 micron processor. Suganth has a B.S. from the College of Engineering Guindy (Anna University), Chennai, India. Suganth is with Intel’s ATOM processor group in Austin, TX.

Jeff Cobb

obtained his MS degree in Fall 2007. Jeff’s work was on efficient computatation of multi-node logic optimization in logic synthesis. Jeff obtained his B.S. from Texas A&M University. Jeff is currently with Texas Instruments, in Houston, TX.

Ekambavanan Sasidharan

obtained his M.S. degree in Summer 2007. Sasidharan’s work was on techniques to reduce the energy and energy-delay product in serial data communication, as well as custom VLSI implementaiton of MIMO sphere decoding algorithms. Sasidharan was co-advised by Prof. K Narayanan. Sasidharan has a B.S. from the College of Engineering Guindy (Anna University), Chennai, India. Sasidharan is currently with Link-A-Media in Santa Clara, CA.

Karandeep Singh

obtained his M.S. candidate in Spring 2007. Karandeep’s work was on techniques to perform sensitizable timing analysis of VLSI circuits, in the presence of data-dependent delays. Karandeep has a B.S. from Punjab Engineering College, Chandigarh, India. Karandeep is currently with Texas Instruments, in Houston, TX.

Salman Gopalani

obtained his Honors B.S. candidate in ECE. Salman’s Honors thesis explores techniques to perform low-NRE structured ASIC design using very simple primitive gates. Salman is currently with National Instruments in Austin, TX.

Prospective Students:

If you are interested in pursuing studies in VLSI, please

send me email . Include test scores, undergraduate grades and class rank, information about projects conducted and your degree goal. Please do not send Word documents, rather send this information in ASCII text or PDF format. Thanks!

External Service:

Invited to serve as an external referee for a Czech Science Foundation grant. I was requested to serve as a referee in June 2018.

Invited to serve as an external referee for the tenure case of a faculty member at the University of Missouri, Kansas City. I was requested to serve as an external referee in Spring 2018.

Invited to serve as Track Chair for the Logic Track for the International Conference on Computer-Aided Design (ICCAD) 2018. I was invited to serve as Track Chair in Spring 2018. Declined due to health reasons.

Invited to serve as Track Chair for the Logic Track for the International Conference on Computer-Aided Design (ICCAD) 2017. I was invited to serve as Track Chair in Spring 2017. Declined due to health reasons.

Invited to serve as Track Chair for the Logic Track for the Design Automation Conference (DAC) 2017. I was invited to serve in late 2016.

Invited to serve as a panelist for ICCAD 2016, for the panel titled “Challenges and Opportunities of Stochastic Computing in the Dusk of Moore’s Law and the Dawn of Big Data”, Declined due to health reasons.

Invited to serve as Track Chair for the Logic Track for the International Conference on Computer-Aided Design (ICCAD) 2016. I was invited to serve as Track Chair in Spring 2016

Invited to serve on the Technical Program Committee (TPC) for the Design Automation Conference (DAC) 2016. I was invited to serve on the EDA5 track (RTL/Logic Level and FPGA Synthesis, Design and Testing)

Invited to serve as Track Chair for the Logic Track for the International Conference on Computer-Aided Design (ICCAD) 2015. I was invited to serve as Track Chair in Spring 2015

Invited to serve on the Technical Program Committee (TPC) for the Design Automation Conference (DAC) 2015. I was invited to serve on the Logic Synthesis track.

Invited to serve on the Technical Program Committee (TPC) of the 28th International Conference on VLSI Design, Bangalore, India in 2015. I was invited to join the TPC in August 2014.

Invited to serve as Technical Program Committee (TPC) co-Chair, EDA Track, for the 21st IEEE International Conference on Electronic Circuits and Systems (ICECS), 2014. I was invited to serve as co-Chair in July 2014.

Invited to serve on the Technical Program Committee (TPC), Design Automation Conference (DAC) 2014. I served on the EDA6 track “High-level and Logic Synthesis and FPGA”.

Invited to serve as Special Sessions Co-Chair for the 57th IEEE Midwest Symposium on Circuits and Systems (MWSCAS) 2014. Also serving on the organizing committee for this conference.

Invited to serve as a Review Committee Member (RCM) for the IEEE International Symposium on Circuits and Systems (ISCAS) 2014.

Invited to serve as Panel Chair for the 2nd IEEE Texas Workshop on Integrated Systems Exploration (TexasWISE), 2014. Also serving on the organizing committee for this workshop.

Invited to serve on the Advisory Committee, for the Hot Topics in Physical Informatics (HotPI) Workshop, 2013.

Invited to serve as Co-Chair for the IEEE International Conference on Electronics, Circuits, and Systems (ICECS) 2013. I served as co-chair for the “VLSI Systems, Applications and Computer Aided Design” track.

Invited to serve as a Panel Chair for the “Models and High-Speed Simulation” session, 15^th ACM/IEEE System Level Interconnect Prediction (SLIP) Workshop 2013, Austin, TX. June 2, 2013.

Invited to join the Technical Program Committee (TPC), The 1st Workshop on Modeling of Biological Systems (MoBS) 2013, Austin, TX. June 2013.

Invited to serve on the ACM Transactions on Design Automation of Electronic Systems (TODAES) best paper committee, March 2013.

Invited to serve as Poster Chair for the 1st IEEE Texas Workshop on Integrated System Exploration (TexasWISE) 2013, Winedale, TX. March 2013. Also served on the organizing committee for this workshop.

Associate Editor, ACM Transactions on Design Automation of Electronic Systems (TODAES). Invited to serve in this capacity in February 2012. I will cover papers in the area of Logic, RTL and behavioral synthesis for a 3-year term.

Lead Guest Editor, VLSI Design. Invited in 2012 to serve as a lead Guest Editor for a Special Issue of VLSI Design.

Invited to join the Editorial Board, MDPI Journal of Electronics, May 2011.

Associate Editor, IEEE Transactions on Computers. I served in this position from 2010 to 2011.

Chair, ACM/SIGDA Logic/RTL Synthesis Technical Committee. I was invited to serve on this committee, from June 2009-2010.

Area Editor (Electronics Design) for the book “GPU Computing Gems”. I was invited to serve as Area Editor in 2009.

Member, Technical Program Committee, IEEE International Workshop on Logic Synthesis (IWLS) 2005-07, 2010. Invited to join this committee in 2004.

Member, Technical Program Committee, Design Automation and Test in Europe (DATE) conference, 2010. I was invited to join the DATE TPC for Track D13 (Logic and Technology Dependent Synthesis for Deep-Submicron Circuits).

Member, selection committee for “ACM Best Ph.D. Dissertation Award in EDA for 2009”, starting February 2010.

Track Chair for Logic Synthesis track, IEEE International Conference on Computer-Aided Design (ICCAD) 2009-10. I was invited to chair the Logic Synthesis track in Spring 2009.

General Chair, IEEE International Workshop on Logic Synthesis (IWLS-09).

Member, Technical Program Committee, International Symposium on Quality Electronic Devices (ISQED) 2009, 2010.

Publicity Co-chair, ACM/IEEE Great Lakes Symposium on VLSI (GLS-VLSI), 2009. Invited to serve as Publicity Co-chair in 2008.

Panel Chair, International Test Synthesis Workshop (ITSW), 2009. Invited to serve on the ITSW committee in 2008.

Technical Program Committee Chair, IEEE International Workshop on Logic Synthesis (IWLS-08). I was invited to join this committee in 2007.

Track Co-chair, IEEE International Symposium on Circuits and Systems (ISCAS) 2008-10. I was invited to co-chair the “Computer Aided Network DEsign” (CANDE) track of ISCAS in 2007.

Member, Technical Program Committee, IEEE International Conference on Computer Aided Design (ICCAD) 2007, 2008, 2009. I was invited to join this committee in 2007.

Member, Technical Program Committee, DesignCon, 2007-2009.

Member, Technical Program Committee, IEEE Great Lakes Symposium on VLSI (GLSVLSI) 2008-10. I was invited to join this committee in late 2007.

Review Committee Member (RCM), IEEE International Symposium on Circuits and Systems (ISCAS) 2007. I was invited to serve as an RCM for the “Computer Aided Network DEsign” (CANDE) track.

Track Co-chair, IEEE International Conference on Computer Design (ICCD-07). I was invited to co-chair the “Test and Methodologies” Track of ICCD in 2007.

Technical Program Committee Member, IEEE International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS), 2004-06. Invited to join this committee in 2003.

Member, Technical Program Committee, IEEE International Conference on Computer Communications and Networks (ICCCN-04). Invited to join this committee in 2003.

Invited to serve as Session Chair for several conferences including the International Conference on Computer Aided Design (ICCAD 2008), Great Lakes Symposium on VLSI (GLSVLSI) 2008,International Test Synthesis Workshop (ITSW) 2007, the International Symposium on Circuits and Systems (ISCAS 2006, 2007), the Asia-South Pacific Design Automation Conference (ASPDAC 2006), the Design Automation Conference (DAC) 2005, the International Conference on Networking (ICON-03), and the Design Automation Conference (2005).

Reviewed a large number of technical papers for numerous technical journals and conferences (1993-2004). Reviews include IEE Transactions (Computers and Digital Techniques), IEEE Transactions on VLSI, IEEE Transactions on CAD of ICs and Systems, Electronic Letters, IEEE Journal of Solid-State Circuits, International Conference on VLSI Design, Design Automation Conference (DAC), International Symposium on Low-Power Electronic Design (ISLPED), Great Lakes Symposium on VLSI (GLS-VLSI), International Conference on Computer-Aided Design (ICCAD), International Conference on Computer Design (ICCD), International Symposium on Circuits and Systems (ISCAS), European Design Automation Conference (Euro-DAC-96), and International Test Conference (ITC).

University and ECE Departmental Service:

Serving on the ECE Hiring Committee (Jan 2018 – present). I have been participating by reviewing faculty applications, meeting faculty candidates, and helping decide on hiring decisions for tenure-track as well as professional faculty

Serving on the Computer Engineering Curriculum Committee (CECC), Fall 2017 – present.

Invited to serve on the College-level “High Performance Computing” (HPC) search committee. I was invited to serve on this committee by Dr. Georghiades in Spring 2015.

Helped the ECE undergraduate recruiting efforts by presenting a talk on the benefits of an ECE degree, to about 100 freshman students who were considering ECE during their entry to major.

Helping undergraduate recruiting by helping conduct a laboratory session in the revamped “ECE Summer Enrichment Workshops” week in July, 2014. In this laboratory, students will learn about ECE by developing a solar car.

On the request of the ECE Department Head, I am initiating a “ECE Pizza Friday” in Spring 2014, in which students will attend a monthly evening meeting hosted by the ECE Department, to showcase the career opportunities that an ECE graduate enjoys. This will be continued in Fall 2014, when all incoming undergraduates will join TAMU with no declared major.

Serving on the TAMU College of Engineering “Emerging Technologies Advisory Council”, (ELTAC), since 2014.

Presentation at Aggieland Saturday (2014). I attended a faculty panel session in which prospective students and their parents asked questions about the TAMU ECE Department.

New Course Development (Spring 2014). I have been working on developing a new undergraduate course. In this course, students will design, synthesize, simulate, place, route, and tape out a digital Integrated Circuit (IC). The course will be a senior elective course. Course Laboratory Redesign (Spring-Summer 2014). I am working on converting the laboratory exercises of two courses, ECEN 248 (Digital Systems Design) and ECEN 449 (Microprocessor Systems Design) to a mobile laboratory station environment, using mobile test equipment from National Instruments.

New Course Development (Spring 2014). I have obtained permission from the Department Head of the ECE Department to initiate a course (a pass/fail, 1 credit course for sophomores or seniors) in which I will discuss career issues. The course will cover life lessons that are important for a healthy career, including life-long learning, networking, people skills, career choices and self-improvement. The lectures will be augmented by visits from industry leaders who will be able to share their career lessons with the students. This course is under development and will be submitted for approval in Spring 2014.

Represented the ECE Department in the College of Engineering initiative to foster closer research ties with the ECE Department at the Indian Institute of Technology, Kanpur, India. Visited IIT Kanpur in 2013 to help identify possible areas of research synergy.

Serving on the ECE Distinguished Speaker Committee, as a representative of the CE group, starting Spring 2013.

Serving on the Computer Engineering Curriculum Committee as the representative of the CE group, starting 2013.

Helped migrate the ECEN 248 laboratory from a Windows platform to a Linux platform (Summer 2011).

Served as the College of Engineering representative for the Friends of India Network (FIN) (2010 – 11).

Served as the representative for ECE in the college level IT committee, to help reduce costs by shared services (2010 – present).

TAMU ECE Scholarship Committee Member, starting February 2010.

Serving as a Faculty Mentor under TAMU’s Network Mentoring Program (NMP) (2009 – present).

Serving on the ECE Undergraduate Studies Committee as the representative of the CE group, starting 2009.

ECE Unix Committee (2008-2014). Along with two other faculty, I am helping provide recommendations for the upgrade and maintenance of the ECE Unix computing infrastructure. I am serving as the chair of this committee since 2009.

Presentation at Discover ECE day (2008-09). Presented a talk to prospective TAMU Engineering students and their parents. The talk titled “What does a Computer Engineer do?” covers courses, research and job prospects in the Computer Engineering area after a B.S. degree in CE from TAMU.

Texas A&M University, assisting in ABET Certification (Spring 2008, Spring 2009, Spring 2013, Spring 2014). Provided data and analysis results for the ECEN 449 course, for ABET certification purposes. Will be providing similar data for Spring 2009.

Redesigned Laboratories for ECEN 248 (Summer 2008). Along with Dr. Choi, I helped to substantially redesign the laboratories for ECEN 248 (Introduction to Digital Systems Design), and make them more current and technically relevant.

Texas A&M University, Qatar. Visited our ECE Department at TAMU-Q during January 2008, to demonstrate the laboratory exercises that we had developed for ECEN 449, to the faculty and laboratory coordinators at TAMU-Q.

Texas A&M University, designed and developed the website for the Computer Engineering group, 2007. Along with my colleague Dr. Alex Sprintson, we developed a new website for the CE group (<ahref=”http://cegroup.ece.tamu.edu”>http://cegroup.ece.tamu.edu).

Course Redesign, ECEN 449 (Summer 2007). Along with Dr. Reddy, I helped to redesign the laboratories and lectures for ECEN 449 (Microprocessor Systems Design).

Presentation at Aggieland Saturday (2007-09). Presented a 15-minute talk to prospective TAMU Engineering students and their parents. The talk covered courses, research and job prospects in the Computer Engineering area after a B.S. degree in CE from TAMU.

Graduate Admissions, Computer Engineering group (2006-2009). Along with a colleague, I help screen graduate applicants for the Computer Engineering group, and make admissions decisions.

Member, ECE Distinguished Visitor Committee (Fall 2005). I served on this committee from Fall 2005 through Fall 2006.

Texas A&M University, ECE faculty interviews, 2004-12. I have made special efforts to attend all ECE faculty hiring candidate seminars, and spend time with ECE faculty candidates. I have provided my feedback to the ECE Department Head, to help ensure that we hire the best faculty.

Texas A&M University, participated in ABET Certification for the Computer Engineering program, 2004-05. The certification process went through flawlessly. My course was used by the ABET personnel to interview the students.

Was invited to be a panelist on a panel discussion on “How to Search for an Academic Job”, Texas A&M University, Fall 2004. Informal advising of undergraduates. Some of my undergraduate and graduate students frequently solicit my input on their courses, career choices and technology trends. Encouraging undergraduates in ELEN 248, ELEN 449 and ELEN 454 to consider pursuing graduate school. Most of them enjoy this discussion very much, since they were not familiar with the option of continuing studies in graduate school. Advised TAMU EE undergraduates Rob Hammond and Anshul Gupta, under the URA program

(2004-05).

Member, Dissertation and Thesis Committee for several Texas A&M students. The students include Hari Sankar (EE, Ph.D.), Ekpe Orafur (EE, Ph.D.), Taekwon Jee (ME, M.S.), Seraj Ahmad (CS, M.S.), Nitin Nangre (ECE, Ph.D.), Kiran Gunnam (ECE, Ph.D.), Ganesh Venkataraman (EE, Ph.D.), Rohit Singhal (EE, Ph.D.), Rupak Samanta (CS, Ph.D.), Maja Knezev (EE, Ph.D.), Zarko Djekic (EE, Ph.D.), Tae Kim (CS, Ph.D.), Meng Shi (EE, M.S.), Jing Sun (EE, M.S.) and John Kocurek (EE, M.S.).

University of Colorado, ECE VLSI Group Ph.D. Preliminary Exam Committee. Since I joined CU, I had been on the VLSI Group Ph.D. Preliminary Exam Committee. I had been involved in conducting about 15 preliminary exams to date. I chaired this committee in 2003, and in 2004 as well.

Member, Graduate Admissions Committee, Department of ECE, CU Boulder (2000 – 2002). Reviewed files and recommended graduate students for admissions. Proposed methods to improve the quality of admitted ECE graduate students. Visited top international schools to encourage high-quality graduate students to apply to the ECE department. Pointed out that we were emphasizing undergraduate GPA too heavily in our graduate admissions process, which is error prone since the undergraduate GPA is estimated in many cases. Recommended and helped implement methods to advertise ECE more aggressively, to ensure that we get quality applicants.

Book review of “Cross-talk Avoidance Techniques in VLSI”, Kluwer Academic Publishers, 2002.

University of Colorado, ECE faculty hiring (2000 – 2002). Provided detailed feedback on all faculty candidates to the Hiring Committee to support the effort of hiring quality faculty. I have met with and attended the seminars of most of the ECE faculty candidates since my arrival at CU.

University of Colorado, ECE Technical Reports (2000 – 2001) When I joined the ECE department, there was no mechanism for faculty to create Technical Reports for their research work. I recommended this to our Chair, and worked with the ECE staff to bootstrap this effort.

University of Colorado, participated in ABET Certification for the ECE Department by providing statistical information about exams and homework from the ECEN 4703 course.

Book review of “Introduction to VLSI Circuits and Systems” by John Uyemura (John Wiley and Sons Publishers), 2001.

Contributed to the release of VIS, a formal verification tool that is developed and distributed by the VLSI group under the direction of Prof Fabio Somenzi. VIS-1.4 was released in Summer 2001 and VIS-2.0 was released in Fall 2002. I have worked on code review, bug fixes and several low-level tasks related to the release.

Member, Dissertation and Thesis Committee for the following CU students: Chao Wang (ECE, Ph.D.), HoonSang Jin (ECE, Ph.D.), Bing Li (ECE, Ph.D.), Adrian Michalicek (ME Ph.D.), Sandeep Dhar (ECE Ph.D.), Yin Yan (ECE Ph.D.), Se-Ho You (ECE Ph.D.), Garrett Holthaus (ECE, M.S.), In-Ho Moon (ECE Ph.D.), Benjamin Patella (ECE M.S.), Balakrishna Kumthekar (ECE Ph.D.), Stephen Gallant (ECE M.S.), Nwanua Elumeze (ECE M.S.), Subramoni Parameswaran (ECE M.S.), Jay Plucienkowski (ECE M.S.), Matthew Lovell (ECE M.S.).

Computing infrastructure of the CU VLSI CAD group: Along with Prof. Fabio Somenzi, I had worked on upgrading the hardware and software infrastructure of the VLSI research laboratory. I had been instrumental in obtaining educational licenses for Rational Software products, which are critically important for us to be able to develop quality software releases from the VLSI group.

Technical Advisor, Accelicon, Inc. (2009-10). Invited to join the Technical Advisory Board of Accelicon, a Silicon Valley company specializing in SPICE model card extraction for circuit simulation. My role was to advise the company in areas relating to the use of GPUs to accelerate their products.

Technical Advisor, Nascentric, Inc. (2008-09). Invited to join the Technical Advisory Board of Nascentric, a company specializing in fast circuit simulation. My role was to advise the company in areas relating to the use of GPUs to accelerate their products.

Technical Advisor, InMage Systems, Inc., Milpitas, CA (2002-06). Invited to join the Technical Advisory Board of SV Systems, a Storage-area Networking (SAN) start-up company specializing in data recovery. My role was to advise the company in areas relating to VLSI design and implementation of relevant ICs.

Faculty Advisor, ITU Ventures, Beverly Hills, CA (2002-04). My role was to advise the ITU personnel about the viability of business proposals in the areas of VLSI Design and CAD.

Technical Advisor, Jasmine Networks, Inc., Santa Clara, CA (2000-01). Invited to join the Technical Advisory Board of Jasmine Networks, an optical networking startup company. My involvement included advice on VLSI issues, including system-level high-speed I/O issues, crosstalk immune bus design, and advice on VLSI design and fabrication.

Recommended to the ECE Department Chair at the University of Colorado, to conduct an “Industrial Visitor Day”, where we would showcase our ECE research and network with the members of the local industry to share our results, and also possibly develop research collaborations with industry. This was implemented in April 2000.

Responsible for responding to user queries about SIS (1993-99). SIS (Sequential Interactive System) is a logic synthesis and optimization system developed at the CAD group at the University of California, Berkeley.

Conducted the Computer-Aided Design Seminar at UC Berkeley (1997-98). Tasks involved inviting and hosting international guests at the seminars, and coordinating the seminars. Reviewed grant proposals for California MICRO grants (1997).

Involved in industrial consulting with Silicon Valley companies (1994-95). Consultant for SUN microsystems’ CAD group as well as their UltraSPARC group in the area of CAD algorithms and issues. Conducted a week-long series of lectures on state-of-the-art CAD algorithms. The focus was SIS, a logic synthesis and optimization tool developed at UC Berkeley. The audience was a group of practicing engineers from the corporate CAD group and the UltraSPARC microprocessor design groups.

Weekly Schedule

Teaching Schedule :

• ECEN 449/749 (Microproressor System Design)
• Lecture: M + W 5:45 p.m. – 6:45 p.m.
• Office Hours: T 5:30 p.m. – 6:30 p.m. on Zoom
• ECEN 689-609: Special Topics in Scalable Distributed Consensus
• Lecture: M + W 4:10 p.m.– 5:25 p.m.
• Office Hours: T 4:30 p.m. – 5:30 p.m. on Zoom

Research Meetings Schedule:

Monday:

• 1:00 p.m.– 2:00 p.m.— SPKgroup Huddle
• 2:00 p.m.– 4:00 p.m.— ASU+TAMU meeting

Tuesday:

• 11:00 a.m. – 12:00 p.m.— Kushagra
• 1:00 p.m.– 2:00 p.m.— Cheng-yen
• 2:00 p.m.– 3:00 p.m.— RTML
• 4:00 p.m.– 5:00 p.m. — Kunal FTL
• 5:00 p.m. – 6:00 p.m.— Pranay

Wednesday:

• 10:00 a.m. – 11:00 a.m. — Georgios/Sarma
• 11:00 a.m. – 12:00 p.m.— Kyle/Conner Wireless VDD
• 1:00 p.m. – 2:00 p.m.— Kyler SAU

Thursday:

• 11:00 a.m. – 11:30 a.m. — Gaurav RIC
• 11:30 a.m. – 12:00 p.m.— JNL huddle
• 1:00 p.m.– 2:00 p.m.— Joellen
• 2:00 p.m.– 3:00 p.m.— Kunal Ladder

Friday:

• 9:15 a.m. – 10:15 a.m. — CESG Seminar
• 10:30 a.m. – 11:00 a.m. — 449/749 TA Huddle
• 11:30 a.m. – 12:30 p.m. — ECE Seminar
• 12:30 p.m.– 1:30 p.m.— CESG Faculty meeting
• 6:00 p.m. – 7:00 p.m.— SPKgroup social

Travel Schedule (tentative)

• No planned travel due to COVID

Administrative Contact:

• Please contact Vickie Winston in case of doubt:

• E-mail: vwinston@.tamu.edu
• Phone: (979) 459-5005