Department of Electrical and Computer Engineering

The Computer Engineering and Systems Group

Clocking in VLSI Design

 


Clock PLL and clock network design is a very important step in VLSI design, particularly in deep sub-micron technologies, in which processing variations make it harder to design reliable clocking for an IC. Our work in VLSI clocking has included papers on dynamic de-skewing approaches for a H-tree clock network (using a single phase detector), which can reduce skew from 300ps to 3ps. We have also developed approaches to design extreme high speed free-running as well as phase-locked standing wave resonant clocking rings. Unlike existing ring-based resonant traveling wave clocking approaches which exhibit a phase change around the ring, our approach does not suffer from this problem. Also, there have been no approaches to phase lock a resonant oscillator, something which we are able to achieve by a novel coarse and fine tunable oscillator.

 

We have also developed techniques to design radiation hardened clocks – focus sing on not only the analog PLL, but also the local clock regeneration buffers.

Publications, patents and artefacts:

  • “Clock distribution scheme using coplanar transmission lines”, Cordero, Khatri. Design Automation, and Test in Europe (DATE) Conference 2008, 10-14 March, Munich, Germany, pp. 985-990. Traditional ring based resonant (rotary) clocks produce clock signals with varying phase along the ring. This paper presents a ring based standing wave resonant clock oscillator, which achieves extreme high speeds, low power consumption and constant phase around the ring. Presentation slides.
  • “A PLL Design based on a Standing Wave Resonant Oscillator”, Karkala, Bollapalli, Garg, Khatri. IEEE International Conference on Computer Design (ICCD) 2009, Lake Tahoe, CA. October 4-7, 2009. In this paper, we present an extreme high frequency clock PLL with lock range between 6GHz and 9GHz. The VCO is a low power ring based standing wave oscillator, and is controlled in two modes (a coarse tuning mode and a fine tuning mode).
  • “Interconnected Tile Standing Wave Resonant Oscillator based Clock Distribution Circuits”, Mandal, Karkala, Khatri, Mahapatra. 24th International Conference on VLSI Design, Chennai, India. Jan 2-7, 2011. This paper reports on techniques to synchronize multiple standing wave ring-based resonant oscillators, as a means to perform clock distribution over a large chip, using ring-based resonant clocking techniques.
  • “A Dynamically De-skewable Clock Distribution Methodology”, Jayakumar, Kapoor, Khatri. IEEE Transactions on Very Large Scale Integration (TVLSI), vol. 16, number 9, Sept 2008, pp. 1220-1229. This paper presents a dynamic clock de-skewing approach for an H-tree clock network. It uses a single phase detector for the entire chip, and is able to deskew a clock signal by two orders of magnitude.
  • “An Automated Approach for Minimum Jitter Buffered H-tree Construction”, Mandal, Jayakumar, Bollapalli, Khatri, Mahapatra. 24th International Conference on VLSI Design, Chennai, India. Jan 2-7, 2011. In this paper, we employ a dynamic programming approach to realize a minimum-jitter clock distribution network.
  • “A Novel Clock Distribution and Dynamic De-skewing Methodology”, Kapoor, Jayakumar, Khatri. International Conference on Computer-Aided Design (ICCAD), Nov 2004, pp. 626-631. In this paper, we present a dynamic clock de-skewing technique, which can deskew a clock network to 3ps from a initial skew of 300ps, with 35% area overhead and a 5% power improvement compared to a non-deskewed network. Presentation slides.
  • “Practical Techniques to Reduce Skew and its Variations in Buffered Clock Networks”, Venkataraman, Jayakumar, Hu, Li, Khatri, Rajaram, McGuinness, Alpert. International Conference on Computer-Aided Design (ICCAD) 2005, Nov 6-10, San Jose, CA, pp. 592-596. This paper presents a skew reduction approach for link-based buffered clock networks. It achieves a skew reduction of 47%, with an improvement in skew yield from 15% to 73%.
  • “SEU Hardened Clock Regeneration Circuits”, Dash, Garg, Khatri, Choi. International Symposium on Quality Electronic Design (ISQED) San Jose, CA. Mar 16-18 2009. This paper presents a radiation hardened clock regenerator, which eliminates radiation induced clock races, and reduces radiation induced clock skew to 30ps, for deposited charge values up to 150fC.
  • “A Radiation Tolerant Phase Locked Loop Design for Digital Electronics”, Kumar, Karkala, Garg, Jindal, Khatri. IEEE International Conference on Computer Design (ICCD) 2009, Lake Tahoe, CA. October 4-7, 2009. In this paper, we present a radiation hardened analog PLL, in which every node is radiation hardened by using a novel split output design approach. The worst case radiation induced jitter is 18%. The PLL requires 16 cycles to lock after the worst case radiation event, a significant improvement over previous radiation hardened PLLs.