Leakage Reduction and Modeling

 

 
In recent times, power due to leakage is becoming comparable to dynamic power in ICs. Given the significant contribution of leakage to the power consumption of the entire VLSI IC, we have focused on several approaches to reduce and model leakage in VLSI designs.

 

Among our leakage modeling approaches, we have developed an Arithmetic Decision Diagram (ADD) based approach to compute the leakage histogram of a design. This can be used to select among several designs which have the same minimum (or maximum) leakage, but different leakage distributions. Also, we have developed two techniques to find the input vector that minimizes leakage in a design while considering process variations.

On the circuit level, we have proposed design approaches which achieve extremely low leakage. When compared to MTCMOS, our approach has comparable leakage, lower area and delay, and complete leakage predictability. Reverse body bias (RBB) reduces leakage but for high RBB, leakage increases due to Band-to-band Tunneling. We have developed a closed loop circuit to find the optimal RBB to minimize leakage. We have also developed approaches to find the leakage minimizing input vector while simultaneously modifying the logic gates. Finally leakage increases with temperature, which in turn increases the temperature. In the FPGA context, we have developed a design-specific approach to quickly and accurately iterate this dependence until convergence.

Publications, patents and artefacts:

• “A Simultaneous Input Vector Control and Circuit Modification Technique to Reduce Leakage with Zero Delay Penalty”, Jayakumar, Khatri. ACM Transactions on Design Automation of Electronic Systems, 2010. In this paper, we reduce leakage by modifying the circuit so as to minimize leakage during standby. The key advantage of this approach is that leakage is reduced without a delay penalty.
• “An ASIC Design Methodology with Predictably Low Leakage, using Leakage-immune Standard Cells”, Jayakumar, Khatri. International Symposium on Low Power Electronics and Design (ISLPED-03), Seoul, Korea, Aug 2003, pp. 128-133. In this paper, we present a low leakage circuit design approach which achieves similar leakage reductions as MTCMOS, but with predictable standby leakage as well as 17% reduced area overhead and 3% improved speed compared to MTCMOS. Presentation slides.
• “An Algorithm to Minimize Leakage through Simultaneous Input Vector Control and Circuit Modification”, Jayakumar, Khatri. Design Automation and Test in Europe (DATE) Conference 2007, April 16-20, Nice, France, pp. 618-623. In this paper, we present an approach to minimize leakage by simultaneously choosing the optimal leakage minimizing vector while making circuit changes to minimize leakage. A 30% improvement in leakage is achieved, with a 2.5% delay improvement and a 23% area increase. Presentation slides.
• “A Predictably Low Leakage ASIC Design Style”, Jayakumar, Khatri. IEEE Transactions on Very Large Scale Integration, vol. 15, number 3, March 2007, pp. 276-285. In this paper we present a low leakage design approach which uses specialized standard cells. Our approach is faster (by 3%) and requires lower area (by 17%) than MTCMOS, with very similar leakage improvements.
• “A Self-adjusting Scheme to Determine the Optimum RBB by Monitoring Leakage Currents”, Jayakumar, Dhar, Khatri. Design Automation Conference (DAC) 2005, Anaheim, CA, June 13-17, pp. 43-46. Leakage reduces with increased reverse body bias (RBB) but for very high RBB, Band-to-band Tunneling (BTBT) increases leakage. In this paper, we present a circuit to find the optimal reverse body bias point automatically across process and temperature variations. Presentation slides.
• “Closed-Loop Modeling of Power and Temperature Profiles of FPGAs”, Gulati, Khatri, Li. ACM/SIGDA International Symposium on Field Programmable Gate Arrays (FPGA). Monterey, CA. Feb 22-24 2009, pp. 287. Increased temperature increases leakage, which in turn increases chip temperature. In this paper, we model this effect to convergence in an FPGA design context. This approach can be used to estimate the worst case chip temperature in a design-specific manner for FPGAs. Our estimated worst case temperature is within 1% of that achieved by a full-chip 3D temperature estimation tool. Presentation slides.
• “A Probabilistic Method to Determine the Minimum Leakage Vector for Combinational Designs in the Presence of Random PVT Variations”, Gulati, Jayakumar, Khatri, Walker. Integration, the VLSI Journal, vol. 41, number 3, May 2008, pp. 399-412. In this paper, we present an efficient method to find the minimum leakage vector (MLV) for a design using signal probabilities. Our method includes the effect of process variations, achieving a 6% improvement in leakage, with significantly lower runtimes compared to an approach based on random simulations
• “Minimum Leakage Vector Computation Using Weighted Partial MaxSAT”, Singh, Gulati, Khatri. 2010 IEEE International Midwest Symposium on Circuits & Systems (MWSCAS), Seattle, WA, Aug 1-4, 2010. In this paper, we present a weighted partial max-SAT approach to determine the MLV under processing variations, for a combinational design. We show that the approach improves the leakage results achieved by the state of the art approach by 4%.
• “An Algebraic Decision Diagram (ADD) Based Technique to find Leakage Histograms of Combinational Designs”, Gulati, Jayakumar, Khatri. International Symposium on Low Power Electronic Design (ISLPED) 2005, August 8-10, San Diego, CA, pp. 111-114. In this paper, we present an ADD based technique to generate the leakage histogram of a design. This technique can be used to find the maximum and minimum leakage as well.
• “A Probabilistic Method to Determine the Minimum Leakage Vector for Combinational Designs”, Gulati, Jayakumar, Khatri. IEEE International Symposium on Circuits and Systems (ISCAS), May 21-24 2006, Kos, Greece, pp. 2241-2244. In this paper, we present a fast, efficient method to find the minimum leakage vector (MLV) for a design. Signal probabilities are used to choose the best gate whose leakage should be fixed next, and a SAT solver is employed to guarantee that consistent decisions are made. Presentation slides.
• “Minimizing and Exploiting Leakage in VLSI Design”, Jayakumar, Paul, Garg, Khatri. Monograph published by Springer Publishers. 1st edition, 2010. 214p. ISBN 978-1-4419-0949-7. The book provides a comprehensive coverage of our work on leakage and sub-threshold circuits. This is also listed in the “Extreme Low Power/Energy System Design” section.