CESG Seminar: Dr. JV Rajendran

Friday, November 17, 2023
10:20 a.m. – 11:10 a.m. (CST)
ETB 1020

Dr. JV Rajendran
Associate Professor | Department of Electrical and Computer Engineering | Texas A&M University

Title: “Hardware Fuzzing — Why? What? How?“

Talking Points:

Do you trust your Verilog code?
Do you want to learn how to hijack a chip?
What keeps CHIP designers up at night?

Abstract
Hardware is at the heart of computing systems. For decades, software was considered error-prone and vulnerable. However, recent years have seen increased attacks exploiting hardware vulnerabilities and exploits, which even traditional software-based protections cannot prevent. In this talk, I will describe what hardware vulnerabilities look like in hardware “programming languages,” such as Verilog and VHDL. Then, I will explain a new and radical approach called hardware fuzzing for finding these vulnerabilities. Finally, I will detail how these new fuzzing techniques can be efficiently combined with existing functional verific

ation and validation approaches.

Biography
Dr. Jeyavijayan (JV) Rajendran is an Associate Professor and an ASCEND Fellow in the Department of Electrical and Computer Engineering at Texas A&M University. He obtained his Ph.D. degree from New York University in August 2015. His research interests include hardware security and computer security. His research has won the NSF CAREER Award in 2017, ONR Young Investigator Award in 2022, the IEEE CEDA Ernest Kuh Early Career Award in 2021, the ACM SIGDA Outstanding Young Faculty Award in 2019, the Intel Academic Leadership Award, the ACM SIGDA Outstanding Ph.D. Dissertation Award in 2017, and the Alexander Hessel Award for the Best Ph.D. Dissertation in the Electrical and Computer Engineering Department at NYU in 2016 along with several best student paper awards. He organizes and has co‐founded Hack@DAC, a student security competition co-located with DAC, and SUSHI.

More Information on Dr. JV Rajendran: HERE