Click on CESG Poster Event 2023 (tamu.edu) to see list of presenters and more information!
CESG SEMINAR: Aditya Arun
Friday, May 12, 2023
11:00 a.m. – 12:00 p.m. (CST)
Fishbowl (WEB 333), In-Person Presentation Only
Aditya Arun, PhD Student
Center of Wireless Communications (CWC) and Contextual Robotics Institute (CRI)
University of California, San Diego
Title: “Leveraging WiFi for Robust and Resource-Efficient SLAM”
Talking Points:
- Simultaneous localization and mapping (SLAM) issues such as errors in odometry or visual sensor measurements, and “Loop closures”
- Perceptual aliasing, loop closure failures, and deployments on small form-factor hardware
- Incorporation of Wi-Fi sensors within existing SLAM systems
Abstract
Indoor robots can increasingly deliver value in diverse industry segments, including logistics, security, and construction. This demand has consequently increased the importance of robust simultaneous localization and mapping (SLAM) algorithms for indoor robots. This robustness is typically provided by fusing information from visual sensors (LiDARs or cameras) with proprioceptive sensors (odometers or IMUs). However, visual sensors can be sensitive to perceptual aliasing, visually dynamic environments, and changing lighting conditions, resulting in failures in SLAM predictions.
In this talk, I will present WiFi radios as camera-like sensors capable of circumventing these issues and develop a real-time SLAM system to provide drift-free trajectory updates. We build our system with off-the-shelf components and evaluate it over four large-scale datasets in three indoor environments, traveling a cumulative distance of over 1500 m. Through these extensive evaluations, we find employing WiFi-based sensing provides a 6x improvement over purely relying on odometry. Additionally, we see a 4x reduction in compute and memory consumption compared to state-of-the-art Visual and Lidar SLAM systems.
Biography
Aditya Arun is a fourth-year Ph.D. student at the University of California, San Diego, advised by Dinesh Bharadia. He is part of the WCSNG group, the Center for Wireless Communications (CWC), and the Contextual Robotics Institute (CRI). His larger research vision is to incorporate WiFi and other wireless technologies as sensing modalities to improve the world of robotics and enable robotics to solve real-world problems. His research interests span wireless sensing, robotics, signal processing, and networking. Previously, he completed his B.S. from the University of California, Berkeley.
More on Aditya Arun: http://wcsng.ucsd.edu/aarun/
More on CESG Seminars: HERE
Please join on Friday, 5/12/23 at 11:00 a.m. in the Fishbowl (WEB 333).
CESG Seminar: Vasudev Gohil
Friday, April 28, 2023
3:50 – 4:50 p.m. (CST)
ETB 1020 or Zoom (see syllabus or email list for link)
Vasudev Gohil
CE PhD Student
Dept. of Electrical and Computer Engineering; Computer Engineering
Texas A&M University
Title: “Reinforcement Learning for Hardware Security ”
Talking Points
- Security threats such as hardware Trojans due to a globalized integrated circuits supply chain
- Using reinforcement learning to detect hardware Trojans efficiently and effectively
- Using reinforcement learning to evaluate hardware Trojan detection techniques accurately
Abstract
Reinforcement learning (RL) has shown great promise in solving problems in novel domains, e.g., marketing, chip placement, and matrix multiplication. In this talk, I will discuss another area that has just begun to reap the powers of RL: hardware security. In particular, I will discuss two of our recent works that use RL to address the threat of hardware Trojans (HTs) in integrated circuits. HTs are malicious logic added by adversaries to harm integrated circuits. They pose a significant threat to critical infrastructures and have been the focus of much research.
In the first part of the talk, I will present a reinforcement learning (RL) agent that returns a minimal set of patterns most likely to detect HTs. Our experimental results demonstrate the efficacy and scalability of our RL agent, which significantly reduces the number of test patterns while maintaining or improving coverage compared to state-of-the-art techniques. In the second part of the talk, I will discuss how we play the role of a realistic adversary and question the efficacy of existing HT detection techniques by developing an automated, scalable, and practical attack framework. Our framework uses RL to evade eight detection techniques across two HT detection categories, demonstrating its agnostic behavior.
Using the example of HTs, our work highlights the potential of RL in solving hardware security problems. The talk will conclude with a discussion of future directions for research in this area.
Biography
Vasudev Gohil is pursuing a Ph.D. in Computer Engineering at Texas A&M University in College Station, Texas. His research interests lie at the intersection of machine learning and hardware security. He is keenly interested in examining and developing IP protection techniques and applying reinforcement learning techniques for security. Before his doctoral studies, Vasudev received a Bachelor of Technology degree in Electrical Engineering with minors in Computer Science from the Indian Institute of Technology Gandhinagar.
More on Vasudev Gohil: https://gohilvasudev.wixsite.com/website
More on CESG Seminars: HERE
Please join on Friday, 4/28/22 at 3:50 p.m. in ETB 1020 or via Zoom.
Zoom option: Links and PW in syllabus or found in email announcement.
CESG Seminar: Archana Bura
Friday, March 31, 2023
3:50 – 4:50 p.m. (CST)
Zoom (see syllabus or email list for link)
Archana Bura
PhD Candidate, Spring 2023
Dept. of Electrical and Computer Engineering
Texas A&M University
Title: “Constrained Reinforcement Learning for Wireless Networks ”
Talking Points
- Challenges in learning under real world problems with constraints
- Developing CRL algorithms for two real world resource allocation problems under constraints
- Safe exploration in learning a generic Constrained MDP
Abstract
In this talk, I will discuss how we efficiently applied reinforcement learning methods for real world problems. I consider two motivating real world problems: Resource allocation for Media streaming at the Wireless edge, and Resource block allocation in an Open RAN system. Under throughput, latency and resource constraints, these systems can be modeled by Constrained Markov Decision Processes (CMDPs). Since these systems have complex dynamics, a constrained reinforcement learning (CRL) approach is attractive for determining an optimal control policy. Applying off-the-shelf RL algorithms yields better results compared to naive solutions, but these algorithms need a lot of samples to train or have high complexity. We overcome these issues by providing CRL methods that efficiently utilize the structure in the problem. Motivated by these results, we study the fundamental “safe exploration” problem in a generic CRL, and propose a safe RL method that does not violate constraints during the learning process with high probability.
Biography
Archana Bura is a PhD candidate at Texas A&M University’s Department of Electrical and Computer Engineering, where she specializes in constrained reinforcement learning. Her research centers around implementing RL for real world problems, where safety is critical, by developing algorithms and theory of constrained reinforcement learning that leverage structure to enhance the learning process.
More on Archana Bura: HERE
More on CESG Seminars: HERE
Please join on Friday, 3/31/22 at 3:50 p.m. via Zoom.
Zoom option: Links and PW in syllabus or found in email announcement.
CESG Seminar: Peipei Zhou
Friday, April 21, 2023
3:50 – 4:50 p.m. (CST)
ZOOM
Peipei Zhou
Assistant Professor
Dept. Electrical and Computer Engineering
University of Pittsburgh
Title: “CHARM: Composing Heterogeneous AcceleRators for Matrix Multiply on Versal ACAP Architecture”
Talking Points
- Which platform beats 7nm GPU A100 in energy efficiency? AMD Versal ACAP (FPGA+AI Chip)!
- How to program AMD Versal ACAP, i.e., FPGA + AI Chip within the same chip die for deep learning applications in 10 lines of code? Use CHARM!
Abstract
Dense matrix multiply (MM) serves as one of the most heavily used kernels in deep learning applications. To cope with the high computation demands of these applications, heterogeneous architectures featuring both FPGA and dedicated ASIC accelerators have emerged as promising platforms. For example, the AMD/Xilinx Versal ACAP architecture combines general-purpose CPU cores and programmable logic (PL) with AI Engine processors (AIE) optimized for AI/ML. An array of 400 AI Engine processors executing at 1 GHz can theoretically provide up to 6.4 TFLOPs performance for 32-bit floating-point (fp32) data. However, machine learning models often contain both large and small MM operations. While large MM operations can be parallelized efficiently across many cores, small MM operations typically cannot. In our investigation, we observe that executing some small MM layers from the BERT natural language processing model on a large, monolithic MM accelerator in Versal ACAP achieved less than 5% of the theoretical peak performance. Therefore, one key question arises: How can we design accelerators to fully use the abundant computation resources under limited communication bandwidth for end-to-end applications with multiple MM layers of diverse sizes? In this talk, we will discuss CHARM framework to compose multiple diverse MM accelerator architectures working concurrently towards different layers within one application. CHARM includes analytical models which guide design space exploration to determine accelerator partitions and layer scheduling. To facilitate the system designs, CHARM automatically generates code, enabling thorough onboard design verification. We deploy the CHARM framework for four different deep learning applications, including BERT, ViT, NCF, and MLP, on the AMD/Xilinx Versal ACAP VCK190 evaluation board. Our experiments show that we achieve 1.46 TFLOPs, 1.61 TFLOPs, 1.74 TFLOPs, and 2.94 TFLOPs inference throughput for BERT, ViT, NCF, MLP, respectively, which obtain 5.40x, 32.51x, 1.00x and 1.00x throughput gains compared to one monolithic accelerator.
Biography
Peipei Zhou is an assistant professor of the Electrical Computer Engineering (ECE) department at the University of Pittsburgh. She has over 10 years of experience in hardware and software co-design. She has published 20+ papers in top-tier IEEE/ACM computer system and design automation conferences and journals including FPGA, FCCM, DAC, ICCAD, ISPASS, TCAD, TECS, TODAES, IEEE Micro, etc. The algorithm and tool proposed in her FCCM’18 paper have been realized in the commercial Vitis HLS (high-level synthesis) compiler from Xilinx (acquired by AMD in Feb 2022). Her work in FPGA acceleration for deep learning won the 2019 Donald O. Pederson Best Paper Award from the IEEE Council for Design Automation (CEDA). Her work in cloud-based application optimization won the 2018 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS) Best Paper Nominee and her work in FPGA acceleration for computer vision won the 2018 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) Best Paper Nominee. Before joining Pitt, she worked as a full-time staff software engineer in a start-up company and led a team of 6 members to develop CNN and MM kernels in the deep learning libraries for two generations of AI training application-specific integrated circuit (ASIC) chip products.
More on Dr. Zhou:
Homepage: https://peipeizhou-eecs.github.io/
Google Scholar: https://scholar.google.com/citations?user=px_jwFgAAAAJ&hl=en
More on CESG Seminars: HERE
Please join on Friday, 4/21/22 at via Zoom (see emails or syllabus for link and password)