Vickie Winston

Friday, November 10, 2023
10:20 a.m. – 11:10 a.m. (CST)
ETB 1020

Dr. Neena Iman
Director of the O’Donnell Data Science and Research Computing Institute (DSRCI)
Southern Methodist University (SMU)

Title: “Future of Data Science: HPC+AI+Beyond-Moore“

Abstract 

The computing ecosystem is at an inflection point with many disruptive technologies merging together. With the debut of exascale supercomputers recently, the architecture of the next generation of HPC platforms is being discussed in the scientific community. The definition of HPC has changed. HPC is no longer just about floating-point operations, but also about the ability to ingest and process huge amounts of data. The traditional HPC applications/workloads are benefiting from the incorporation of AI and machine learning. Additionally, with the plateauing of Moore’s law, there is tremendous momentum in Beyond-Moore technologies, particularly in quantum. This talk will discuss the future of data science in this rapidly changing technology landscape.

Biography
Dr. Neena Iman is the inaugural Director of the O’Donnell Data Science and Research Computing Institute (DSRCI) at Southern Methodist University (SMU), a position key to the university’s commitment to data-focused education and next-gen computational research. The DSRCI also serves as the gateway to SMU’s HPC environment. Before joining SMU,

Neena Imam served as the Director of Strategic Researcher Engagement at NVIDIA corporation, the industry-leader in GPU computing and AI/ML research. In this role, Neena worked with academic researchers to enable GPU-accelerated and AI/ML applications development. Before NVIDIA, Neena served as a distinguished scientist and the Director of Research Collaboration in the Computin

g and Computational Sciences Directorate at Oak Ridge National Laboratory (ORNL). At ORNL, Neena performed research in HPC, as well as next-generation microelectronics and Post Moore computing.  Neena is the author/co-author of many scientific articles, served as an invited speaker and panelist at many conferences, and is active in professional organizations to promote research and education in HPC and AI.

Neena holds a Doctoral degree in Electrical Engineering from Georgia Institute of Technology, with Master’s and Bachelor’s degrees in the same field from Case Western Reserve University and California Institute of Technology, respectively. Neena also served as the Science and Technology Fellow for Senator Lamar Alexander in Washington D.C. (2010-2012). Neena is a senior member of IEEE,  served as an IEEE officer for multiple years, and is the founding Chair of ACM SIGHPC ASCAN (Accelerated Scalable Computing and ANalytics) chapter.

More on CESG Seminars: HERE

Please join on Friday, 11/10/23 at 10:20 a.m. in ETB 1020.

Friday, October 27, 2023
10:20 a.m. – 11:10 a.m. (CST)
ETB 1020

Doug Burger
Technical Fellow | Microsoft

Title: “The New AI Computing Stack“

Talking Points:

• Emergent capabilities of large language models, built on top of deep learning
• The intersection of traditional computing and the AI stack
• The evolution of the AI stack, key challenges and problems
• Future implications of the tandem working of the traditional and AI stacks

Abstract
We have entered a new era of computing.  Large language models, built on top of deep learning, have shown surprising emergent capabilities.

These capabilities, such as rich semantic understanding, ability to generate content, and ability to plan and reason, will change how people use computers and for what computers can effectively be used.

This AI stack is effectively a second general class of computing that intersects with the traditional computing stack in surprising and compelling ways.

In this talk I will discuss how the AI stack is evolving, some of the key challenges that we are currently facing, and the most important problems to be working on in this area.

If we are successful, and these challenges are solved, these two computing stacks working in tandem will transform and up-level humanity’s capabilities.

Biography
Doug Burger is a Technical Fellow at Microsoft.  From 1999-2008, he served on the Computer Sciences faculty at UT-Austin, where he co-led the TRIPS project with Steve Keckler.

From 2008-2018, he was a researcher in Microsoft Research, where he led the Catapult and Brainwave projects, which both shipped at large scale in Microsoft’s datacenter infrastructure.

From 2018-2022 he served as a product executive in Azure’s new hardware group, leading teams architecting large-scale AI infrastructure.

In 2023, he returned to Microsoft Research to help drive advanced thinking in AI-based computing.  He is a Fellow of the ACM and the IEEE.

More on CESG Seminars: HERE

Please join on Friday, 10/27/23 at 10:20 a.m. in ETB 1020.

Friday, October 20, 2023
10:20 a.m. – 11:10 a.m. (CST)
ETB 1020

Abu Sebastian
Distinguished Research Scientist, IBM Research – Europe

Title: “Analog In-Memory Computing for Deep Learning Inference“

Talking Points: 

• What is analog in-memory computing (AIMC)?
• How mature is AIMC?
• What are the key open research topics and what’s next for AIMC?

Abstract
I will introduce analog in-memory computing based on non-volatile memory technology with a focus on the key concepts and the associated terminology. Subsequently, a multi-tile mixed-signal AIMC chip for deep learning inference will be presented. This chip fabricated in 14nm CMOS technology comprises 64 AIMC cores/tiles based on phase-change memory technology. It will serve as the basis to delve deeper into the device, circuits, architectural and algorithmic aspects of AIMC. Of particular focus will be achieving floating point-equivalent classification accuracy while performing the bulk of computations in the analog domain with relatively less precision. I will also present an architectural vision for a next generation AIMC chip for DNN inference. I will conclude with an outlook for the future.

Two papers that may be of interest:

1. “Y2023_legallo_NatureElectronics.pdf”

2. “Y2020_sebastian_NatureNano.pdf”

Biography
Abu Sebastian is one of the technical leaders of IBM’s research efforts towards next generation AI Hardware and manages the in-memory computing group at IBM Research – Zurich. He is the author of over 200 publications in peer-reviewed journals/conference proceedings and holds over 90 US patents.  In 2015 he was awarded the European Research Council (ERC) consolidator grant and in 2020, he was awarded an ERC Proof-of-concept grant. He was an IBM Master Inventor and was named Principal and Distinguished Research Staff Member in 2018 and 2020, respectively. In 2019, he received the Ovshinsky Lectureship Award for his contributions to “Phase-change materials for cognitive computing”. In 2023, he was conferred the title of Visiting Professor in Materials by University of Oxford. He is a distinguished lecturer and fellow of the IEEE.

More on Abu Sebastian: https://research.ibm.com/people/abu-sebastian

More on CESG Seminars: HERE

Please join on Friday, 10/20/23 at 10:20 a.m. in ETB 1020.

Friday, October 13, 2023
10:20 a.m. – 11:10 a.m. (CST)
ETB 1020

Arif Merchant
Research Scientist @ Google

Title: “Research Directions in Google Storage“

Talking Points: 

• How does Google Storage work?
• How do you lay out data across tens of thousands of disks, dozens of device types, with wildly varying failure rates and capacities, while keeping them all well utilized, and the data safe?
• What are the open research questions in Cloud Storage?

Abstract
Google’s Cloud is a very large consumer of storage, and these storage systems are geographically distributed, multi-layered, heterogeneous, and complex. We present a high-level overview of Google’s storage systems, the common challenges faced by storage at Google, and explore several research directions for managing and optimizing the resources used. We will touch upon topics in layout, encoding, and new storage technologies. We will conclude with a discussion of some open questions.

Biography
Arif Merchant is a Research Scientist at Google and leads the Storage Analytics group, which studies interactions between components of the storage stack. His interests include distributed storage systems, storage management, and stochastic modeling. He holds the B.Tech. degree from IIT Bombay and the Ph.D. in Computer Science from Stanford University. He is an ACM Distinguished Scientist.

More on CESG Seminars: HERE

Please join on Friday, 10/13/23 at 10:20 a.m. in ETB 1020.

Friday, September 8, 2023
10:20 a.m. – 11:10 a.m. (CST)
ETB 1020

P. R. Kumar
Professor at Dept. of Electrical & Computer Engineering
Texas A&M University

Title: “Security of Cyber-Physical Systems: Theory and Applications of the Dynamic Watermarking Method”

Talking Points: 

• How to protect our critical infrastructure from cyber-attacks?
• How to secure the power grid, oil refineries, autonomous vehicles?
• What sort of guarantees can be provided?

Abstract

The coming decades will see the large scale deployment of networked cyber–physical systems to address global needs in energy, water, health care, transportation, etc. However, as recent events have shown, such systems are vulnerable to cyber attacks.  We present a general purpose technique, called “dynamic watermarking,” for detecting malicious activity in networked systems of sensors and actuators. It provides a provable guarantee of detection of any non-zero power attack. This method has been implemented in several systems of interest. We present the results of attacks on an autonomous automobile, a grid-tied photovoltaic system, a process control system, and a tethered helicopter. We also present the results of simulation studies of attacks on larger scale systems such as the power grid, through attacks on its automatic gain control loop, and attacks on the Tennessee-Eastman model, an open source benchmark that has been developed for the purpose of evaluating process control technology used in industries such as chemical plants and oil refineries. [Joint work with Kenny Chour, Tong Huang, Hasan Ibrahim, Gopal Kamath, Jaewon Kim, Woo Hyun Ko, Tzu-Hsiang Lin, Jorge Ramos-Ruiz, Bharadwaj Satchidanandan, Lantian Shangguan, Bin Wang, Prasad Enjeti, Swaminathan Gopalswamy, and Le Xie].

Biography

Dr. Kumar has a B.Tech. from IIT Madras (1973), and D.Sc. from Washington University (1977). After serving in the Math Department, UMBC (1977-84), and ECE and CSL, UIUC (1985-2011), he joined Texas A&M. He is a member of the U.S. NAE, the World Academy of Sciences, and the Indian NAE. He was awarded an honorary doctorate by ETH, Zurich. He has received the Alexander Bell Medal of IEEE, the IEEE Field Award for Control Systems, and the Outstanding Contribution Award of ACM SIGMOBILE. He has also received the Eckman Award of AACC, the Ellersick Prize of IEEE COMSOC, the Infocom Achievement Award, and the SIGMOBILE Test-of-Time Paper Award. He is a Fellow of IEEE, an ACM Fellow, and Fellow of IFAC. He was awarded the Distinguished Alumnus Award from IIT Madras, Alumni Achievement Award from Wash U, and Drucker Eminent Faculty Award from CoE, University of Illinois. His current research focus includes reinforcement learning, security, privacy, power systems, automated transportation, unmanned aerial vehicle traffic management, millimeter wave 5G, snd cyber-physical systems.

More on P.R. Kumar: P. R. Kumar (tamu.edu)

More on CESG Seminars: HERE

Please join on Friday, 9/8/23 at 10:20 a.m. in ETB 1020.

Friday, September 1, 2023
10:20 a.m. – 11:10 a.m. (CST)
ETB 1020, In-Person Presentation Only

Sunil Khatri
Professor at Dept. of Electrical & Computer Engineering
Texas A&M University

Title: “Flash – the ‘Overlooked’ Technology”

Talking Points: 

• Flash technology has historically been used for non-volatile memory
• Can flash be used for digital, analog and mixed-signal circuits also?
• This talk posits that it can, and thus holds great promise for VLSI circuit design broadly

Abstract

Flash has been the workhorse technology for non-volatile memories for many years now. In this talk, I show that flash technology can be used to design a variety of general-purpose circuits, both digital and analog. This is demonstrated via case studies that demonstrate two styles of flash-based ASIC design (including a secure variant), flash-based convolutional neural network accelerators (both analog and digital variants), flash-based in-memory computing designs, as well as flash-based analog circuits like DACs and LDOs. Through these studies, we demonstrate several advantages of flash-based designs over conventional CMOS designs,and argue that flash is an overlooked technology in digital and analog design. Some of these advantages of flash are not present in CMOS, such as performance tunability, the ability to counteract circuit aging, the control of speed binning, and the ability to mitigate process variations.

Based on our findings, we posit that the programmability, robustness, stability, and maturity of flash give it a significant edge over the class of “emerging” technologies, making flash a viable technology to eventually replace CMOS.  We hope that our body of work on flash will encourage further research and deployment in the arena of scaling flash to smaller process node geometries, thereby allowing flash to become a key technology for digital and analog circuits in the future.

Biography

Dr. Sunil P Khatri received his PhD from UC Berkeley, his MS from UT Austin, and his BS degree from IIT Kanpur (India). He currently serves as a Professor in ECE at Texas A&M University. His research areas are VLSI IC/SOC design (including hardware-based machine intelligence, secure hardware design, classical and quantum logic synthesis, radiation tolerant design and fast clocking), algorithm acceleration using custom hardware, FPGAs and GPUs, and interdisciplinary extensions of these topics to other areas like communication, DSP, IoT and genomics.

He has co-authored the first papers in many areas, resulting in impactful contributions that changed industrial practice in the areas of regular fabric-based VLSI design approaches, cross-talk canceling CODECs to eliminate on-chip and off-chip crosstalk in VLSI bus interconnect, GPU-based acceleration of VLSI CAD algorithms, and high-speed off-chip output drivers with self-adjusting impedance. Dr. Khatri has over 280 peer reviewed publications. Among these papers, 5 received a best paper award while 7 others received best paper nominations.

More on Sunil Khatri: Sunil Khatri (tamu.edu)

More on CESG Seminars: HERE

Please join on Friday, 9/1/23 at 10:20 p.m. in ETB 1020.

Friday, May 12, 2023
11:00 a.m. – 12:00 p.m. (CST)
Fishbowl (WEB 333), In-Person Presentation Only

Aditya Arun, PhD Student
Center of Wireless Communications (CWC) and Contextual Robotics Institute (CRI)
University of California, San Diego 

Title: “Leveraging WiFi for Robust and Resource-Efficient SLAM”

Talking Points: 

• Simultaneous localization and mapping (SLAM) issues such as errors in odometry or visual sensor measurements, and “Loop closures”
• Perceptual aliasing, loop closure failures, and deployments on small form-factor hardware
• Incorporation of  Wi-Fi sensors within existing SLAM systems

Abstract
Indoor robots can increasingly deliver value in diverse industry segments, including logistics, security, and construction. This demand has consequently increased the importance of robust simultaneous localization and mapping (SLAM) algorithms for indoor robots. This robustness is typically provided by fusing information from visual sensors (LiDARs or cameras) with proprioceptive sensors (odometers or IMUs). However, visual sensors can be sensitive to perceptual aliasing, visually dynamic environments, and changing lighting conditions, resulting in failures in SLAM predictions.

In this talk, I will present WiFi radios as camera-like sensors capable of circumventing these issues and develop a real-time SLAM system to provide drift-free trajectory updates. We build our system with off-the-shelf components and evaluate it over four large-scale datasets in three indoor environments, traveling a cumulative distance of over 1500 m. Through these extensive evaluations, we find employing WiFi-based sensing provides a 6x improvement over purely relying on odometry. Additionally, we see a 4x reduction in compute and memory consumption compared to state-of-the-art Visual and Lidar SLAM systems.

Biography
Aditya Arun is a fourth-year Ph.D. student at the University of California, San Diego, advised by Dinesh Bharadia. He is part of the WCSNG group, the Center for Wireless Communications (CWC), and the Contextual Robotics Institute (CRI). His larger research vision is to incorporate WiFi and other wireless technologies as sensing modalities to improve the world of robotics and enable robotics to solve real-world problems. His research interests span wireless sensing, robotics, signal processing, and networking. Previously, he completed his B.S. from the University of California, Berkeley.

More on Aditya Arun: http://wcsng.ucsd.edu/aarun/

More on CESG Seminars: HERE

Please join on Friday, 5/12/23 at 11:00 a.m. in the Fishbowl (WEB 333).