Seminars

Friday, April 12, 2024

10:20 a.m. – 11:10 a.m. (CST)
ETB 1020

Jennifer Dworak
Professor @ Southern Methodist University, Electrical and Computer Engineering

Title: “Keeping Customers Happy (and Safe)! Designing Circuits to Enhance Defect Detection and Avoid Errors and Silent Data Corruption“

Abstract
The impact of failing integrated circuits (ICs) can vary from an annoyance to a catastrophic failure.  Errors in circuit operation may arise due to defects that are present when a circuit is manufactured, latent defects that develop further over time and cause failures early in a circuit’s lifetime, and defects that arise later in the circuit’s lifetime due to aging.  Unfortunately, companies such as Meta have recently found that errors arising from hardware defects are occurring in the field at much higher rates than expected.  New ways of testing and monitoring circuits efficiently and effectively are required.

Biography
Jennifer Dworak is a Professor in the Department of Electrical and Computer Engineering at Southern Methodist University. Her research interests include manufacturing test, hardware security, and the reliability of digital circuits and systems.  She is a recipient of an NSF CAREER Award and a 2012 Ralph E. Powe Junior Faculty Enhancement Award funded by Oak Ridge Associated Universities.  She is a co-author on multiple technical articles, including two papers that won Best Paper Awards from the VLSI Test Symposium and a paper that won a TTTC Naveena Nagi Award.  Prof. Dworak also holds two patents on cybersecurity locks, keys, traps and honeypots and one patent on a laser-powered device for enhanced security.  She has given over 30 invited talks and been an invited panelist at multiple technical meetings in several countries.  Most recently, she has co-led the effort that led to the Texoma Semiconductor Tech Hub, a consortium of 52 organizations led by SMU, being designated as an official EDA Tech Hub. Prof. Dworak holds PhD, MS, and BS degrees in electrical engineering from Texas A&M University in College Station, TX, USA.

For more on Dr. Dworak please see her SMU Website at https://www.smu.edu/lyle/departments/ece/people/faculty-and-staff/jennifer-dworak

Please join on Friday, 4/12/24 at 10:20 a.m. in ETB 1020.

Friday, April 5, 2024

10:20 a.m. – 11:10 a.m. (CST)
ETB 1020

Parthasarathy (Partha) Ranganathan
VP / Technical Fellow | Google

Title: “A 6-Word Story on the Future of Infrastructure: AI-Driven, Software-Defined, Uncomfortably Exciting“

Abstract
We are at an interesting inflection point in the design of computing systems. On one hand, demand for computing is accelerating at phenomenal rates, powered by the AI revolution and ever deeper processing on larger volumes of data, and amplified by smart edge devices and cloud computing. On the other hand, Moore’s law is slowing down. This is challenging traditional assumptions around cheaper and more energy-efficient systems every generation and leading to a significant supply-demand gap for future computing systems. In this talk, we discuss how this current computing landscape motivates a significant rethinking of how we design future infrastructure. We present two broad themes around (1) efficient systems design through custom silicon accelerators and (2) efficient systems utilization through software-defined infrastructure. We will summarize our experience in these areas and discuss key learnings and future opportunities for innovation. Looking ahead, we will highlight some additional grand challenges and opportunities for the community, specifically touching on key themes around agility, modularity, reliability, and sustainability, as well as the disruptive potential of cloud computing, and the opportunities beyond compute, around storage.

Biography
Parthasarathy (Partha) Ranganathan is currently a VP, Technical Fellow at Google where he is the area technical lead for hardware and datacenters, designing systems at scale. Prior to this, he was a HP Fellow and Chief Technologist at Hewlett Packard Labs where he led their research on system and data centers. Partha has worked on several interdisciplinary systems projects with broad impact on both academia and industry, including widely used innovations in energy-aware user interfaces, heterogeneous multi-cores, power-efficient servers, accelerators, and disaggregated and data-centric data centers. He has published extensively (including being the co-author on the popular “Datacenter as a Computer” textbook), is a co-inventor on more the 100 patents, and has been recognized with numerous awards. He has been named a top-15 enterprise technology rock star by Business Insider, one of the top 35 young innovators in the world by MIT Tech Review, and is a recipient of the ACM SIGARCH Maurice Wilkes Award, Rice University’s Outstanding Young Engineering Alumni Award, and the IIT Madras Distinguished Alumni Award. He is one of few computer scientists to have his work recognized with an Emmy award. He is also a Fellow of the IEEE and ACM and has served on the board of directors for OpenCompute.

Please join on Friday, 4/5/24 at 10:20 a.m. in ETB 1020.

Friday, March 22, 2024

10:20 a.m. – 11:10 a.m. (CST)
ETB 1020

Dr. Alok N. Choudhary
Harold Washington Professor, Electrical and Computer Engineering and Computer Science Departments
Northwestern University

Title: “AI for Science”

Abstract
“AI for Science” seeks to explore and develop Machine Learning and Data Mining (“AI”) approaches for accelerating scientific discoveries as well as designs. An example of this is learning from data to build predictive models that can enable exploration of scientific questions without relying upon underlying theory. Given that modern instruments, supercomputing simulations, experiments, sensors and IoT are creating massive amounts of data at an astonishing speed and diversity, “AI for Science” has the potential to significantly accelerate science discoveries. E.g., can AI learn chemistry from data? Or how can AI replace or reduce the need for expensive simulations or experiments to perform discoveries quickly or evaluate a feasible design space? This talk will present some learnings that address some of the questions above using various materials design and discovery and other examples.

Biography
An Dr. Alok Choudhary is Harold Washington Professor in the ECE and CS departments at Northwestern University. He was the founder, chairman and chief scientist of 4C insights, a big data analytics and marketing technology software company (4C was recently acquired by MediaOcean). He received the National Science Foundation’s Young Investigator Award in 1993. He was listed by Adweek in “trailblazers and pioneers in Marketing technologies”. He is a fellow of IEEE, ACM and AAAS and a recipient of the NSF Young Investigator Award. He has published more than 400 papers in various journals and conferences and has graduated 45+ PhD students, including more than 10 women PhDs. He serves on the board or advisory boards of several companies. He is a co-author and co-editor of a recent book “AI for Science: A Deep Learning Revolution”.

Please join on Friday, 03/22/24 at 10:20 a.m. in ETB 1020.

Friday, March 1, 2024

10:20 a.m. – 11:10 a.m. (CST)

Dr. James Caverlee
Professor, Department of Computer Science and Engineering
Texas A&M University

ETB 1020

Title: “Thoughts on Large Language Models: Data Efficiency, Bias, and Long-Tails”

Abstract

In this talk, I will share some recent work from our lab and from Google DeepMind on several big challenges in Large Language Models including: 1) data efficiency: since pre-training LLMs is hugely expensive, can we develop data efficient methods to more intelligently select training examples? 2) bias: while advances in techniques to minimize explicit bias can superficially enable LLMs to avoid the perception of bias, can we indirectly probe LLMs to reveal their intrinsic bias? And develop methods towards mitigating this bias? 3) long-tails: LLMs can demonstrate strong performance on popular concepts, but in many cases there is a gap in the treatment of rare (or tail) concepts. Can we bridge this gap?

Biography

Dr. James Caverlee is a Professor in the Department of Computer Science and Engineering at Texas A&M University and a Visiting Researcher at Google DeepMind. His research focuses on connecting people to information, with an emphasis on algorithms and systems that are trustworthy, resilient, and responsible.

More on CESG Seminars: HERE

Please join on Friday, 03/01/24 at 10:20 a.m. in ETB 1020.

Friday, February 23, 2024

10:20 a.m. – 11:10 a.m. (CST)

Dr. Anand Sivasubramaniam
Distinguished Professor, Department of Computer Science and Engineering
Pennsylvania State University

ETB 1020

Title: “Revisiting Memory Hierarchy Management in the GPU Context”

Abstract

As GPUs become mainstream to take on the computational challenges of Big Data applications, it is increasingly critical that we continue to maintain a steady stream of data flowing into their plentiful computational engines, to sustain their throughput capabilities. Despite on-chip caches and high bandwidth memories, these storage capacities are just not sufficient to hold the large working sets exhibited by Big Data applications close to the computational engines. There are several reasons why this problem is not just more acute in the GPU context, but also requires a different set of solutions than those employed for this decades-old problem in the CPU context. In this talk, apart from highlighting these issues, I will present 2 recent management solutions we have implemented on today’s GPUs. The first explicitly differentiates spatial and temporal locality in pages, and places data selectively in GPU memory and/or its caches based on this differentiation. In the second work, I will show how we have extended the GPU memory hierarchy to spill beyond its memory into host memory, and even into SSDs, and develop a bypass/placement strategy for selectively placing pages.

Biography

Dr. Anand Sivasubramaniam is a Distinguished Professor at Penn State, where he has been on the faculty since 1995, immediately after completing his PhD from Georgia Tech. His research interests are broadly in computer systems, covering both hardware and software aspects towards improving performance, energy efficiencies and system reliability/availability. He has published around 300 articles in highly competitive venues, and his work has been funded by NSF, DARPA, and several industries. He is an ACM and IEEE Fellow, recognized for his work and contributions to power management of computer systems.

More on CESG Seminars: HERE

Please join on Friday, 02/23/24 at 10:20 a.m. in ETB 1020.

Friday, February 9, 2024

10:20 a.m. – 11:10 a.m. (CST)
ETB 1020

Dr. Edward Knightly
Sheafor-Lindsay Professor , Department of Electrical and Computer Engineering
Rice University

Title: “Curved Beams, Flying Metasurfaces, and Emerging Capabilities for 6G”

Abstract

Next generation wireless networks promise unprecedented performance by exploiting wide bandwidths available in millimeter wave to sub-Terahertz spectrum. At such frequencies, transmission is necessary highly directive in order to overcome path loss. In this talk, I will debunk two myths of such networks: the first myth is that intelligent surfaces or smooth specular-reflecting surfaces are required to overcome blocked paths via reflected paths. Instead, I will show the theory and experimental results for curving beams around obstacles. The second myth is that highly directional rooftop backhaul links are inherently immune to interception by an eavesdropper. Instead, I will show the theory and experimental results for intercepting a roof-top sub-THz backhaul link without detection by using a metasurface-equipped UAV.

Biography
Dr. Edward Knightly is the Sheafor–Lindsay Professor of Electrical and Computer Engineering and Computer Science at Rice University. He received his Ph.D. and M.S. from the University of California at Berkeley and his B.S. from Auburn University. He is an ACM Fellow, an IEEE Fellow, and a Sloan Fellow. He received the IEEE INFOCOM Achievement Award, the Dynamic Spectrum Alliance Award for Research on New Opportunities for Dynamic Spectrum Access, the George R. Brown School of Engineering Teaching + Research Excellence Award, and the National Science Foundation CAREER Award. He won eight best paper awards including ACM MobiCom, ACM MobiHoc, IEEE Communications and Network Security, and IEEE INFOCOM. He serves as an editor-at-large for IEEE/ACM Transactions on Networking and serves on the scientific council of IMDEA Networks in Madrid and the scientific advisory board of INESC TEC in Porto. He served as the Rice ECE department chair from 2014 to 2019. His research interests include design, prototyping, and in-the-field demonstration of next generation mobile and wireless networks, with a focus on networking, sensing, and security in diverse spectrum spanning from sub-6 GHz to millimeter wave and terahertz.

More on CESG Seminars: HERE

Please join on Friday, 02/09/24 at 10:20 a.m. in ETB 1020.

Friday, February 2, 2024
10:20 a.m. – 11:10 a.m. (CST)
ETB 1020

Dr. Jiang Hu
Professor, Department of Electrical and Computer Engineering
Texas A&M University

Title: “Chip Power Modeling and Physical Optimization Techniques”

Abstract
Power estimation and physical layout are both critical components in modern chip designs. The first part of this talk will be focused on a lightweight machine learning approach to microprocessor architecture level power modeling, which can be applied in either design-time power estimation or runtime power monitoring. This technique reduces power simulation time from two weeks to a few minutes for an industrial design. It also decreases the area overhead of on-chip power monitoring from 10% to less than 0.2%. The second part is about FPGA placement for CNN circuits. Different from conventional general-purpose methods, this is a customized approach that can make good use of the intrinsic regularity in CNN circuits. This technique reduces wirelength by about 24% compared to an industrial tool and state-of-the-art academic methods. Moreover, it usually leads to significantly reduced routing resource utilization, accelerated placement runtime and improved timing performance.

Biography
Dr. Jiang Hu is a professor in the Department of Electrical and Computer Engineering at Texas A&M University. His research interests include electronic design automation, approximate computing and machine learning for chip designs. He has co-authored more than 250 technical papers, co-invented 10 patents and co-edited a book. He received best paper awards at DAC 2001, ICCAD 2011, IEEE International Conference on Vehicular Electronics and Safety 2018, MICRO 2021 and ASPDAC 2023. He served as the technical program chair and general chair of the ACM International Symposium on Physical Design in 2011 and 2012, respectively. He was named an IEEE fellow in 2016. He was the technical program co-chair for the ACM/IEEE Workshop on Machine Learning for CAD 2023 and will be its general co-chair in 2024.

More on CESG Seminars: HERE

Please join on Friday, 02/02/24 at 10:20 a.m. in ETB 1020.

 

Friday, January 26, 2024
10:20 a.m. – 11:10 a.m. (CST)
ETB 1020

Wantong Li
PhD Candidate, School of Electrical and Computer Engineering
Georgia Institute of Technology

Title: “Efficient, Robust, and Heterogeneous Compute-in-Memory for Edge Intelligence”

Abstract 
Deep neural networks (DNNs) have provided remarkable performance gains in fields spanning computer vision and natural language processing. The increasingly heavier workloads to run DNN models have attracted interdisciplinary efforts to speed up DNN inference, and many of such efforts focus on accelerating the dominant multiply-and-accumulate (MAC) operations. On the hardware front, the disruptive paradigm of compute-in-memory (CIM) aims to process data directly inside memory arrays. Complex arithmetic operations such as MAC can be performed using compute-capable CIM arrays to achieve massive parallelism and unprecedented energy efficiency.

This talk focuses on the IC design and hardware architecture aspects of CIM for executing DNN workloads. The talk first presents a mixed-signal CIM engine that performs parallelized MAC operations inside resistive random-access memory (RRAM) arrays. The RRAM-based CIM chip, fabricated in TSMC 40-nm node, is equipped with circuit designs that ensure PVT-robust operations across a wide spectrum of operating conditions. Next, the unique opportunities to transform computing inside a heterogeneous 3-D (H3D) stack are discussed. An H3D CIM accelerator targeting vision transformer models is shown to gain form factor and energy efficiency enhancements. Finally, low-power portable ultrasound imaging is presented to showcase how CIM can benefit embedded electronics. Through data volume reduction of the ultrasound frontend and a local CIM-based reconstruction accelerator, significant power savings can be achieved for the portable imaging device.

Biography
Wantong Li is a Ph.D. candidate in electrical and computer engineering at the Georgia Institute of Technology. He received a BSEE degree from Washington University in St. Louis in 2015 and a MSEE degree from Columbia University in 2016. From 2017 to 2019, he worked as an IC Design Engineer at Power Integrations. He also held internship positions at AMD, MediaTek, and Roche Diagnostics. He is the recipient of the Georgia Tech ECE INSPIRE Fellowship in 2023. His research centers on memory-centric computing platforms, spanning areas of efficient and robust IC design, heterogeneous 3-D integrated systems, and domain-specific architecture.

 

More on CESG Seminars: HERE

Please join on Friday, 1/26/24 at 10:20 a.m. in ETB 1020.

Friday, January 19, 2024
10:20 a.m. – 11:10 a.m. (CST)
ETB 1020

Dr. Kevin Nowka
Professor of Practice, Department of Electrical and Computer Engineering
Texas A&M University

Title: “Systems and Machine Learning Research for Application in Digital Agriculture“

Abstract 
Agricultural practices developed during the Green Revolution of the 1960s to 1980s are insufficient to deal with future global demands for food, especially with increasing natural resource controls. Digital Agriculture research is allowing for continued improvements in crop yields and crop quality with better management practices and more efficient resource utilization.  This talk will cover how use of large agricultural datasets and modern machine learning allows agricultural researchers and producers to improve predictability of crop health and crop yields in support of improved agricultural management practices. Recent research on integration of ML with crop imaging from drones and satellites for wheat, cotton, and sorghum will be presented. Finally, integration of learning systems into agriculture infrastructure will be described.

Biography
Dr. Kevin Nowka is a Professor of Practice in the Texas A&M University Department of Electrical and Computer Engineering. His research focuses on optimizing computer hardware and software and learning models for data-intensive, cognitive and AI applications.

He received a B.S. in Computer Engineering from Iowa State University in 1986 and M.S. and Ph.D. degrees in Electrical Engineering from Stanford University in 1986 and 1995, respectively.

Previously he was the Director of IBM Research – Austin, one of IBM’s 12 global research laboratories and was the IBM Senior State Executive for Texas. Prior to coming to IBM he was a Member of Technical Staff at AT&T Bell Labs.

Dr. Nowka has been granted 135 US Patents and has over 100 publications.

More on Kevin Nowka
https://www.linkedin.com/in/kevin-nowka-6587715b/ or https://www.researchgate.net/profile/Kevin-Nowka

More on CESG Seminars: HERE

Please join on Friday, 1/19/24 at 10:20 a.m. in ETB 1020.

Friday, December 1, 2023
10:20 a.m. – 11:10 a.m. (CST)
ETB 1020

Dr. Azalia Mirhoseini
Assistant Professor, Department of Computer Science
Stanford University

Title: “Pushing the Limits of Scaling Laws in the Age of Large Language Models“

Abstract 
The recent success of large language models has been characterized by scaling laws – the power law relationship between performance and training dataset size, model parameter size, and training compute. In this talk, we will discuss ways to push the scaling laws even further by innovating across data, models, software and hardware. This includes reinforcement learning from human and AI feedback to improve learning efficiency, sparse and dynamic mixture-of-experts neural architectures for better performance, an automated framework for co-designing custom AI accelerators, and a deep RL method for chip floorplanning used in multiple generations of Google AI’s accelerator chips (TPU). Through these cutting-edge examples, we will outline a full-stack approach that leverages AI to overcome the next set of scaling challenges.

Biography
Dr. Azalia Mirhoseini is an assistant professor of computer science at Stanford University and a senior staff research scientist at DeepMind. Her research interest is developing capable and efficient AI systems that can solve high-impact, real-world problems. Before joining Stanford, Prof. Mirhoseini spent several years in industry, working on frontier generative AI and deep reinforcement learning projects at Anthropic and Google Brain. She has led a diverse portfolio of AI and Systems projects, with publications in Nature, ICML, ICLR, NeurIPS, UAI, ASPLOS, SIGMETRICS, DAC, DATE, and ICCAD. She has received a number of awards, including the MIT Technology Review 35 Under 35, the Best Ph.D. Thesis at Rice University’s ECE Department, and a Gold Medal in the National Math Olympiad in Iran. Her work has been covered in various media outlets, including MIT Technology Review, IEEE Spectrum, The Verge, Times of London, ZDNet, VentureBeat, and WIRED.

More on Azalia Mirhoseini: http://azaliamirhoseini.com/

More on CESG Seminars: HERE

Please join on Friday, 12/1/23 at 10:20 a.m. in ETB 1020.