Publication

G. Choi, R. Iyer, V. Carreno, “Simulated Fault Injection: A Methodology to Evaluate Fault Tolerant Microprocessor Architectures,” IEEE Transaction on Reliability – Special Issue on Experimental Evaluation, Vol, 39, No. 4, pp. 486-491, October 1990.
G. Choi, R. Iyer, R. Saleh, V. Carreno, “A Fault Behavior Model For and Avionic Microprocessor,” Dependable Computing, Editors: A. Avizienis, J. Laprie, pp 177-195, Springer-Verlag, 1990.
G. Choi, R. Iyer, “FOCUS: An Experimental Environment for Fault Sensitivity Analysis,” IEEE Transaction on Computers, Vol. 41, No. 12, pp.1515-1526, December 1992.
H. Cha, E. Rudnick, J. Patel, R. Iyer, G. Choi, “A Fast and Accurate Gate-Level Transient Fault Simulation Environment,” IEEE Transaction on Computer, Vol. 45, No. 11, pp. 1248-1256, November 1996.
S. Hwang, G. Choi, “Selective-Set-Invalidation(SSI) for Soft-Error-Resilient Cache Architecture, “ACM SIGARCH, Computer Architecture News, pp. 32-38, June, 1999
S. Hwang, G. Choi, :RTMS: A Reliability Testing Environment for Off-The-Shelf Memory-Subsystems,” IEEE Design & Test, June, 1999.
B. Min, G. Choi, ” Verification Simulation Acceleration Using Code-Perturbation,” Journal of Electronic Testing and Testing Automation, JETTA, Volume 16, Issue 1, Feb 2000
Rohit Singhal*, Gwan Choi, Rabi N. Mahapatra, “Data Handling Limits of On-Chip Interconnects,” IEEE Transactions on Very Large Scale Integration Systems 16(6): 707-713 (2008)
Garg, Jayakumar*, Khatri, Choi, “Circuit-level Design Approaches for Radiation-hard Digital Electronics,” IEEE transactions on very large scale integration (VLSI) systems, ISSN 1063-8210
Wang, Weihuang; Kim, Euncheol; Gunnam, Kiran K.; Choi, Gwan S., “Low-Power VLSI Design of LDPC Decoder Using Dynamic Voltage and Frequency Scaling for Additive White Gaussian Noise Channels,” Journal of Low Power Electronics, Volume 5, Number 3, October 2009 , pp. 303-312(10)
K.Gunnam, G. Choi and M. Yeary, “A Parallel VLSI Architecture for Layered Decoding for Array LDPC Codes” submitted to the IEEE Transactions on Circuits and Systems-II
A. Selvarathinam, G. Choi, “Design and Analysis of Massively Scaleable Decoder Architecture for Low-Density Parity-Check Codes,” Submitted to The IEEE Transaction on Computer
Z. Yang, G. Choi, “SiEmulation Approach for Verification Acceleration,” Submitted to IEEE Transaction on VLSI
R. Tayade, G. Choi, “Importance Sampling Based Error Gain Analysis,” Prepared for submission to Journal of Pervasive Computing and Communications (JPCC)
E. Kim, G. Choi, “5Gbit LDPC Decoder Implementation Using 910nm CMOS Circuit for DVBS-2,” Prepared for submission to Circuits and Systems II
Sanghoan Chang, Gwan Choi, “Empirical Timing Failure Rate Estimation of CPUs Under Operating Noises,” submitted to Journal of Electronic Testing: Theory and Applications (JETTA)
Sanghoan Chang, Rohit Singhal, Gwan Choi, “Delay Fault Tolerant Design Using Partial Hardware/Time/Information Redundancies,” submitted to IEEE Transactions on VLSI
W. Wang, G. Choi, K. Gunnam, ” Dynamic Energy Scheduling for ASIC Implementation of LDPC Decoder,” prepared for submission to IEEE Transactions on Circuits and Systems-II
Y. Yang, G. Choi, “Low-Power Embedded LDPC-H.264 Joint Decoding Architecture Based on Unequal Error Protection”, submitted to IEEE Journal on Selected Areas in Communications
Bhagawat, Choi, “High Throughput Configurable Soft Output MIMO Detector”, submitted to IEEE Transactions on Circuits and Systems II
Bhagawat, Dash, Choi, “Systolic Like Soft Output Detector for High Order MIMO System”, revision submitted to IEEE Transaction on VLSI Manuscript No. TVLSI-00064-2009
S. Lee, Y. Yang, W. Mu, R. Iyer, G. Choi, D Newell, “Low Power Reliable Network-on-Chip (NoC) Based on Orthogonal Latin Squares,” submitted to IEEE Design & Test of Computers
Bhagawat, Dash, Choi, “Energy Efficient Soft Detector Architecture for SDR Applications”,
Bhagawat, Dash, Choi, “Optimizing the VLSI Architecture for Soft De-mapper in High Order MIMOOFDM Systems”, (Under Preparation)
Bhagawat, Dash, Choi, “VLSI Architecture for High Throughput Runtime Configurable MIMO Detector”,. (Under Preparation)
Praveen Bhojwani, Rohit Singhal, Gwan Choi and Rabi Mahapatra, “Forward Error Correction for On-chip Interconnection Networks,” Unique Chips and Systems, Invited Book Chapter, Publication date: October 2007, CRC Press.
G. Choi, R. Iyer, R. Saleh, V. Carreno, “A Fault Behavior Model For an Avionic MicRoprocessor,” Proceedings of the IFIP International Conference on Dependable Computing for Critical Applications, Santa Barbara, CA, August, 1989
G. Choi, R. Iyer, R. Carreno, “FOCUS: An Experimental Environment for Validation of Fault Tolerant Systems, Case Study of a Jet-Engine Controller,” Proceedings, IEEE ICCD: VLSI in Computers & Processors, Cambridge, MA, October 2-4, 1989.
G. Choi, R. Iyer, J. Patel, “Simulation-Based Reliability Prediction,” SRC TECHON ’90, San Jose, CA, October 15-19, 1990.
V. Carreno, G. Choi, R. Iyer, “Analog-Digital Simulation of Transient-Induced Logic Errors and Upset Susceptibility of Advanced Control System,” NASA Technical Memorandum 4241, November 1990.
G. Choi, R. Iyer, J. Patel, “A Monte-Carlo Simulation Environment for Wear-Out in VLSI Systems,” Proceedings, The Fourth CSI/IEEE International Symposium on VLSI Design (VLSI Design 1991), New Delhi, India, January 4-8, 1991
K. Goswami, G. Choi, R. Iyer, “Design for Dependability,” Proceedings, AIAA Computing in Aerospace 8, Baltimore, MD, October 21-24, 1991. H. Cha, E. Rudnick, G. Choi, J. Patel, R. Iyer, “A Fast and Accurate Gate-Level Transient Fault
Simulation Environment,” Proceedings of The 23rd International Symposium on Fault-Tolerant Computing (FTCS-23), Toulouse, France, June 23-25, 1993.
G. Choi, R. Iyer, “Wear-Out Simulation Environment for VLSI Designs,” Proceedings of The 23rd International Symposium on Fault-Tolerant Computing (FTCS-23), Toulouse, France, June 23-25, 1993.
H. Cha, G. Choi, J. Patel, R. Iyer, “Modeling of Single Event Upsets for Fault-Tolerant System Validation,” Proceedings, AIAA Computing in Aerospace 8, San Diego, CA, October, 1993.
G. Choi, R. Iyer, “Fault Behavior Dictionary for Simulation of Device-level Transients,” Proceedings, IEEE ICCAD-93, Santa Clara, CA, November 7-11, 1993.
G. Choi, R. Iyer, “Software Upset Analysis: A Case Study of the HS1602 Microprocessor,” Proceedings, The Second Asian Test Symposium, Beijing, China, November 17-18, 1993.
T. Tsai, G. Choi, R. Iyer, “Hybrid Fault-Injection Methodology,” International Workshop on Integrating Error Models with Fault Injection, Annapolis, MD, April 25-26, 1994.
G. Ries, G. Choi, R. Iyer, “Device Level Transient Fault Modeling,” Proceedings of The 24th International Symposium on Fault-Tolerant Computing (FTCS-24), Austin, TX, June 1994.
C. Kouba and G. Choi, “A Single Event Upset Evaluation Environment,” Proceedings of the IEEE Radiation Studies Conference, RADSCON-96, Prairie View, TX April 22-23, 1996.
K. Lee, G. Choi, “Fault-Handling Evaluation Simulation,” Proceedings, IEEE CAD-TD, Beijing, China, July, 1996.
C. Kouba and G. Choi, “SEU Analysis of 486DX4 microprocessors,” Proceedings, IEEE NSREC- 97, Snowmass Villiage, CO, July 25-27, 1997.
K. Lee, Gwan Choi, “Fault-Tolerant Component Design: A simulation Assisted Approach,” Proceedings of the Pacific-Rim FTCS, Taipei, Taiwan, November, 1997.
R. Lal, Gwan Choi, “Error and Failure Analysis of a UNIX Server,” High-Assurance Systems Symposium, HASE-98, Orlando, FL, November 1998.
S. Hwang, G. Choi, “Design of Reliable Cache Subsystems,” High-Assurance Systems Symposium, HASE-98, Orlando, FL, November 1998.
S. Hwang, G. Choi, “RTMS: A Reliability Testing Environment for Off-The-Shelf Memory- Subsystem” submitted to the IEEE, International Test Conference, 1998.
B. Min, G. Choi, “Verification Using Dynamic Code Perturbation,” Microprocessor Test and Verifiation Workshop, MTV-98, 1998.
Z. Yang, G. Choi, “Low Power Design Approach for a Multi-Functional Unit,” IEEE Computer Society Annual Workshop on VLSI, Orlando, FL, April, 1999.
E. Daniel, R. Lal, G. Choi, ”Warnings and Errors: A Measurement Study of a UNIX Server,” Brief Paper, FTCS-29, Madison, WI, June, 1999.
E. Daniel, G. Choi, ”TMR For Off-The-Shelf Unix Systems,” Brief Paper, FTCS-29, Madison, WI, June, 1999.
S. Hwang, G. Choi, “Soft-Error Testing of COTS DRAM Components,” IEEE AUTOTESTCON-99, San Antonio, September, 1999.
Z. Yang, G. Choi, “Si-Emulation: System Verification Using Simulation and Emulation,” IEEE International Test Conference, ITC-2000, Santa Clara, June 2000.
Z. Yang, B. Min, G. Choi, “Simulation Using Code-Perturbation: Black- and White-Box Approaches,” IEEE ISQED-2001, San Jose, 2001.
Z. Yang, G. Choi, “An On-Line Testing Approach Using Code-Perturbation, IEEE IOLTW-2001, Taormina, Italy, July, 2001
G. Choi, “DRAM Testing Approaches,” Invited Paper, STAIF-2001, Albuquerque, NM, February, 2001
B. Min, G. Choi, “RTL Functional Verification Using Excitation and Observation Coverage,” IEEE High-Level Design Validation and Test Workshop, Monterey, November 7-9, 2001
D. Mohanty, R. Mahapatra, G. Choi, “A Design Space Exploration Framework in Multiprocessor SoC Co-Design,” Real-Time Embedded Systems Workshop, London, December 3, 2001
B. Min, G. Choi, “ECC: Extended Condition Coverage for Design Verification Using Excitation and Observation,” IEEE Pacific-Rim Dependability Symposium, Seoul, December 16-19, 2001
Selvarathinam, G. Choi, K. Narayanan, E. Kim, “A Massively Scaleable Decoder Architecture for Low-Density Parity-Check Codes,” IEEE International Symposium on Circuits and Systems, Bangkok,
Thailand, May, 2003
A. Selvarathinam, G. Choi, “A Parity Check Matrix Tiling Approach for High Throughput Low Density Parity-Check Decoders,” 2003 Communications Theory Workshop, Mesa, AZ, April, 2003.
A. Selvarathinam, E. Kim, G. Choi: Low-Density Parity-Check Decoder Architecture for High Throughput Optical Fiber Channels,” 21st IEEE International Conference on Computer Design, ICCD 2003, San Jose, CA, 13-15 October 2003
S. Chang, G. Choi, “Delay Failure Rate Estimation: An Experimental Approach,” The 5th IEEE Latin-American Test Workshop, Cartagena, Colombia, March 8-10, 2004.
R. Singhal, G. Choi, P. Koteeswaran, N. Mickler, “SCALEABLE CHECK NODE CENTRIC ARCHITECTURE FOR LDPC DECODER,” IEEE International Symposium on Circuits and Systems, Vancouver, Canada, May, 2004
K.Gunnam, G. Choi and M. B. Yeary, “An LDPC Decoding Schedule for Memory Access Reduction”, IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP 2004), Montreal, Quebec, Canada, May 2004.
R. Tayade, G. Choi, “Simulation Acceleration Technique for Forward-Error-Correction Analysis,” PCC-04, The 2004 International Conference on Pervasive Computing and Communications, Monte Carlo Resort, Las Vegas, Nevada, June 21-24, 2004
E. Kim, G. Choi, “Interconnect Partitioning for VLSI Implementation of LDPC Decoder,” APCC 2004, Sydney, 2004
Rohit Singhal, Gwan Choi and Rabi Mahapatra, “Quantized LDPC Decoder Design for Binary Symmetric Channels”, Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS), 2005
P. Bhagawat, M. Uppal, G. Choi, “FPGA-Based Implementation of Decoder for Array Low-Density Parity Check Codes,” International Conference on Acoustics, Speech, and Signal Processing, Philadelphia, PA, March, 2005
A. Selvarathinam, G. Choi, “Tiling parity-check matrix for Reduced Complexity High Throughput Low-Density Parity-Check Decoders,” The IEEE 2005 Workshop on Signal Processing Systems (SIPS’05), Athens, Greece, on November 2-4, 2005
Euncheol Kim, Gwan S. Choi, “Diagonal Low-Density Parity-Check Code for Simplified Routing in Decoder,” The IEEE 2005 Workshop on Signal Processing Systems (SIPS’05), Athens, Greece, November 2-4, 2005
1.Rohit Singhal, Gwan Choi, Rabi N. Mahapatra, “Programmable LDPC decoder based on the bubble-sort algorithm”, in proc. IEEE VLSI Design 2006, pp. 203-208, January 2006.
Praveen Bhojwani, Rohit Singhal, Gwan Choi, Rabi Mahapatra, “Forward error correction for onchip networks,” Workshop for Unique Chips and Systems (UCAS-2), March 2006.
Rohit Singhal, Gwan Choi, Rabi Mahapatra, “Information theoretic capacity of long on-chip interconnects in the presence of crosstalk,” Proceedings, 7th International Symposium on Quality of Electronic Design (ISQED 2006), San Jose, CA, 27-29 March 2006.
E. Kim, N. Jayakumar, P. Bhagawat, A. Selvarathinam, G. Choi, S. Khatri, “A High-Speed Fully Programmable VLSI Decoder for Regular Low Density Parity Check Codes,” IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP 2006), Toulouse, France, May 2006.
Rajesh Garg, Nikhil Jayakumar, Sunil P. Khatri, Gwan Choi: A design approach for radiation-hard digital electronics. IEEE Design Automation Conference DAC2006, San Francisco, CA, July 2006. Sanghoan Chang, Gwan Choi, “Timing Failure Analysis of Commercial CPUs Under Operating
Stress,” IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems(DFT’06), Washington DC., October, 2006
K.Gunnam, G. Choi, W. Wang, E. Kim, and M.B. Yeary, “Decoding of quasi-cyclic LDPC Codes using On-The-Fly Computation”, 40th Asilomar Conference on Signals, Systems and Computers, October 2006.
Rohit Singhal, Gwan Choi, Rabi Mahapatra, “Information Theoretic Approach to Address Delay and Reliability in Long On-Chip Interconnects,” IEEE ICCAD 2006, San Jose, November, 2006.
Sanghoan Chang, Gwan Choi, “Gate-Level Exception Handling Design for Noise Reduction in High-Speed VLSI Circuits,” IEEE VLSI Design Conference, Bangalore, India, January 2007
K.Gunnam, G. Choi, M.B. Yeary “A Parallel Layered Decoder Architecture for Array LDPC Codes”, IEEE VLSI Design Conference, Bangalore, India, January 2007
K. Gunnam, W. Wang, G. Choi, and M.B. Yeary, “VLSI Architectures for Turbo Decoding Message Passing Using Min-Sum for Rate-Compatible Array LDPC Codes,” Accepted for International Symposium on Wireless Pervasive Computing (ISWPC) 2007, Puerto Rico, Feb 2007.
Weihuang Wang, Gwan Choi, ” Speculative Energy Scheduling for LDPC Decoding,” International Symposium on Quality Electronic Design (ISQED’07), March 2007.
Weihuang Wang, Gwan Choi, “Minimum-Energy LDPC Decoder for Real-Time Mobile Application” Design, Automation and Test (DATE07), Acropolis, Nice, France, April 2007
K.Gunnam, G. Choi, W. Wang, and M.B. Yeary, “Multi-Rate Layered Decoder Architecture for Block LDPC Codes of the IEEE 802.11n Wireless Standard” accepted for IEEE Symposium on Circuits and Systems (ISCAS)-2007, New Orleans, LA, May 2007.
K. Gunnam, G. Choi, and M. Yeary, “A low-power preamble detection methodology for packet based RF modems on all-digital sensor front-ends ,” IMTC 2007 – IEEE Instrumentation and Measurement Technology Conference Warsaw, Poland, May 1–3, 2007
Pankaj Bhagawat, Weihuang Wang, Momin Uppal, Gwan Choi, Zixiang Xiong, Mark Yeary and Alan Harris, “An FPGA Implementation of Dirty Paper Precoder,” Proceedings, IEEE ICC 2007 Wireless Communications Symposium, Glasgow,Scotland, June 2007.
K.Gunnam, G. Choi, M.B. Yeary, and M. Atiquzzaman, “VLSI Architectures for Layered Decoding for Irregular LDPC Codes of WiMax” Proceedings, IEEE ICC 2007 Wireless Communications Symposium, Glasgow,Scotland, June 2007.
Pankaj Bhagawat, Sasidharan Ekambavanan, Gwan Choi, Sunil Khatri, “VLSI Implementation of a Staggered Sphere Decoder Design for MIMO Detection”, Forty Fifth Annual Allerton Conference, September 2007.
Bhagawat, R. Dash, G. Choi, “Architecture for Reconfigurable MIMO Detector and its FPGA Implementation,” Electronics, Circuits and Systems, 2008. ICECS 2008. 15th IEEE International Conference on, Aug. 31 2008-Sept. 3 2008 Page(s):61 – 64P.
Bhagawat, R. Dash, G. Choi, “Dynamically reconfigurable soft output MIMO detector,” Computer Design, 2008. ICCD 2008. IEEE International Conference on, Oct 12-15, 2008, Lake Tahoe, Page(s):68 – 7
Gunnam, K.K.; Choi, G.S.; Yeary, M.B.; Shaohua Yang; Yuanxing Lee, “Next generation iterative LDPC solutions for magnetic recording storage,” Signals, Systems and Computers, 2008 42nd Asilomar Conference on, Publication Year: 2008 , Page(s): 1148 – 1152
Pankaj Bhagawat, Rajballav Dash, Gwan Choi, “High Performance on-the-fly Reconfigurable MIMO Detector”, IEEE Asilomar Conference on Signals, Systems, and Computers, Oct 26-29, Monterey, 2008.
W. Wang, G. Choi, K. Gunnam, ” Low-Power VLSI Design of LDPC Decoder Using DVFS for AWGN Channels,” VLSI Design, 2009 22nd International Conference on, 5-9 Jan. 2009
Pankaj Bhagawat, Rajballav Dash, Gwan Choi,Array Like Runtime Recofigurable MIMO Detectors for 802.11n WLAN: A Design Case Study”, IEEE Asia and South Pacific Design Automation Conference (ASPDAC), Jan 19- 22,2009, Yokohama, Japan
Dash, Garg, Khatri, Choi. “SEU Hardened Clock Regeneration Circuits,” International Symposium on Quality Electronic Design (ISQED) San Jose, CA. Mar 16-18 2009.
Pankaj Bhagawat, Rajballav Dash, Gwan Choi, Systolic Like Soft-Detection Architecture for 4×4 64-QAM MIMO System”, IEEE Design Automation and Test in Europe(DATE), April 20-24,2009, Nice, France
Y. Yang, G. Choi, “Low-Power Embedded LDPC-H.264 Joint Decoding Architecture Based on Unequal Error Protection”, IEEE FutureTech, Busan, South Korea 2010 T. Jain, P. Gratz, A. Sprintson, G. Choi, “Asynchronous Bypass Channels : Improving
Performance for DVFS and GALS NoCs,” IEEE NOCS 2010 R. Rajendran, A. Manivannan, G. Choi, “Adaptive Variable Rate Power Aware LDPC Decoder,” 4th IEEE WoWMoM Workshop on Autonomic and Opportunistic Communications (AOC 2010)
Y. Yang, P. Bhagawat, G. Choi, “Energy Minimization for H.264 Video on Portable MIMO-Video Communication Devices,” IEEE International Symposium on a World of Wireless Mobile and Multimedia Networks
A. Taylor, Y. Yang, G. Choi, “A Position Sensitive Radiation Detector Design Using Silicon Photo-Diode Array,” submitted to IEEE Nuclear and Space Radiation Effects Conference 2010
Y. Yang, A. Taylor, P. Bhagawat, D. Drahorn, G. Choi, “Energy Efficient, Remotely Deployable, and Stacked Wafer-Scale CMOS Radiation Sensor and Network System,” submitted to IEEE Nuclear and Space Radiation Effects Conference 2010.