EE 754 — Advances in VLSI Circuit Design. 

Fall 2008

Instructor:	Sunil P Khatri
Office:		333F WERC
Phone:		979-845-8371
Fax:		979-845-2630
E-mail:		i r t a h k l i n u s (spell backwards, drop spaces) at tamu dot edu
Class time  :	MW 5:45pm - 7:00pm, ZEC 128A 
Office Hours:	MW 1:00pm - 2:00pm 
		or by appointment
Text:		None, course will be taught from lecture notes which are
		posted on this page.  These notes draw from several sources, 
		and can be considered comprehensive. If you prefer to buy a 
		textbook for your reference, you may consider these text books, 
		in order of utility 

		Digital Integrated Circuits - A Design Perspective - Rabaey 
		Principles of CMOS VLSI Design - a systems perspective - Weste and Eshraghian 
		The design and analysis of VLSI circuits - Glasser and Dobberpuhl.


Course Objective

This course covers several aspects of digital circuit design. Starting with device equations, we will delve into several areas of digital circuit design, including recent changes in circuit design styles and future trends in digital circuit design. We will cover different design styles, memory design, leakage power control and exploitation, board level design concepts, and clocking and dynamic compensation of circuit characteristics.

The goal of the class is to take you through a tour of the issues a typical circuit designer in industry deals with, and the design techniques they utilize. The focus is on custom digital VLSI design. At the end of this class, you would have at your disposal an understanding of the analysis techniques and tools that are required for a VLSI circuit designer to effectively function in today’s industry.

The intended audience would be graduate students interested in the techniques and trends in contemporary VLSI circuit design. The course could serve as a starting point for possible research in this area.


Course Prerequisites

Graduate standing, or instructor consent.


Course Outline

        Gate and wire delays and their shift in importance 
        Overview of CMOS device fundamentals 
                DC Characteristics
                AC Characteristics
                Processing overview
        Different circuit design styles 
                NMOS
                Static CMOS
                Dynamic CMOS
                Pass Transistor design
                PLAs
                SOI implications
                GaAs implications
        Memory design fundamentals 
                Types of memory cells
                Design considerations for memory
                3-Dimensional capacitive parasitics.
        Leakage and Power 
                Leakage control approaches
                Computing with leakage currents
        Transmission lines and their modeling 
                On-chip clock nets
                Board nets
        Packaging issues 
                Inductive effects
                Different packaging technologies.
                Economic considerations of different package styles
        Off-chip I/O drivers design considerations
        On-chip clock distribution schemes. 
                H-tree clock distribution
                Dynamic de-skewing of a clock network
        Processing variations and their control 
                On-the-fly variation compensation


Important Logistical Issues

As I indicated in the first lecture, you are responsible to read this page and familiarize yourself with the important logistical information on it.

Please remember that email will be used as an official means of communicating class information to you. You should make sure that the email address that you gave me on the first day of class is a current and functioning address. In case of any changes in your email address, please let me know ASAP.

Per University Regulations, I will allow a student who is absent from class for the observance of a religious holy day to take an examination or complete an assignment scheduled for that day within a reasonable time after the absence, if, not later than the 15th day after the first day of the semester, the student notifies me that they would be absent on which particular days.

If you believe that you have a disability requiring an accomodation, the University provides academic adjustments and auxiliary aids as defined under the law. In such a case, you should register your documentation with the Office of Services for Students with Disabilities before any accomodations are made. Once this office reviews your documentation and verifies your condition, I will make reasonable accomodations.

Remember that plagiarism will not be tolerated and will be dealt with under the Aggie Honor System Office guidelines.


Homework, Exams, and Grading

             20%   5-7 Homework assignments
             40%   Two Midterm Exams
             40%   Course Project (in lieu of Final Exam)

In general you will have one week to do a homework assignment. The due date for each homework will be indicated. A homework turned in one week late will be penalized 50%. A homework turned in later than a week will receive no credit. You are welcome to work together on homework, but you should not turn in identical solutions, or one solution for multiple students.

There will be two open-notes, open-book, midterm exams in this course

There will be a class project in lieu of final exam. The project will involve research and implementation. A list of candidate projects will be circulated about 60 days before the end of the course. Students may choose to do a project not on this list, after consulting with the instructor. In prior offerings of this course, several such class projects have resulted in technical publications at leading conferences. The topic areas of these projects will broadly cover VLSI design and CAD, and not be restricted to VLSI circuit design alone. There will be no penalty for negative results in the project, as long as all theoretical and implementation options are thoroughly explored by the student.

I will grade EE689-608 on a curve.


Lecture Notes

Lecture Notes:

1-dsmconn.pdf .

2-cmos.pdf .

3-strawman.pdf .

4-dcchar.pdf .

5-processing.pdf .

6-acchar.pdf .

7-gaassoi.pdf .

8-spicespace.pdf .

9-cktstyles.pdf .

10-ntkpla.ppt .

10b-seu.ppt .

11-memory.pdf .

12-xline.pdf .

13-leakage-a.ppt .

13-leakage-b.ppt .

14-io-esd.ppt .


Homework and Other Postings

Homework assignments and solutions:

Homework 1 in pdf format .

Homework 2 in pdf format .

Homework 3 in pdf format .


Software Resources

The logic synthesis system SIS and the logic minimization program ESPRESSO are part of the homework problems and the subject of some of the lectures. The student will be given computer accounts on EE machines where the programs are installed. Alternately the programs can be downloaded and installed on the student on their own machines. If you wish to download and install the software on your machine, please let me know.

How to program in SIS .

How to program in SIS using BDDs .

SIS version 1.4 tarball (if you want to compile it on your home machine). .

The links below are for the circuit projects..

spice3f5 tarball with support for bsim4 and bsimsoi model cards (if you want to compile it on your home machine). .

Notes on how to compute linear resistance for a MOSFET (see last 2 pages) .

Notes on transmission lines, and how to compute L and C. .

Notes on using SPICE and SPACE3D. .

100nm BSIM process cards (PMOS and NMOS). . –>


Sunil P Khatri / Texas A&M University /