Leakage Reduction and Modeling

Leakage Reduction and Modeling

 

In recent times, power due to leakage is becoming comparable to dynamic power in ICs. Given the significant contribution of leakage to the power consumption of the entire VLSI IC, we have focused on several approaches to reduce and model leakage in VLSI designs.

Among our leakage modeling approaches, we have developed an Arithmetic Decision Diagram (ADD) based approach to compute the leakage histogram of a design. This can be used to select among several designs which have the same minimum (or maximum) leakage, but different leakage distributions. Also, we have developed two techniques to find the input vector that minimizes leakage in a design while considering process variations.

On the circuit level, we have proposed design approaches which achieve extremely low leakage. When compared to MTCMOS, our approach has comparable leakage, lower area and delay, and complete leakage predictability. Reverse body bias (RBB) reduces leakage but for high RBB, leakage increases due to Band-to-band Tunneling. We have developed a closed loop circuit to find the optimal RBB to minimize leakage. We have also developed approaches to find the leakage minimizing input vector while simultaneously modifying the logic gates. Finally leakage increases with temperature, which in turn increases the temperature. In the FPGA context, we have developed a design-specific approach to quickly and accurately iterate this dependence until convergence.

Publications, patents and artefacts: