Department of Electrical and Computer Engineering

The Computer Engineering and Systems Group

Testing and ATPG

 


Automatic Test Pattern Generation (ATPG) is an important problem in VLSI testing, enabling a designer to automatically create tests to check for manufacturing defects in a design. We have developed a methodology to speed up combinational ATPG using multi-level Don’t Cares. The resulting tool is about 30% faster than a commercial ATPG tool (with no aborted faults unlike the commercial tool). In addition, We have also worked on the design of scan flip-flops in a manner that reduces test power by 14%. Another line of work explores the use of pulsed flip-flops in enhanced scan as well as launch-on-shift flip-flops, which are 14% faster than traditional enhanced scan cells. We have also accelerated fault dictionary generation on the Graphics Processing Unit (GPU) platform, obtaining a 20X speedup (80X projected if we use a 8-GPU server) over a serial algorithm. Finally, we have developed a fault simulator on the GPU, which is 35X faster (estimated 240X speedup with a 8-GPU server) than a CPU-based implementation, as well as a fault table generator on the GPU.

 

Publications, patents and artefacts:

  • “Efficient SAT-based Combinational ATPG using Multi-level Don’t-Cares”, Saluja, Khatri. International Test Conference (ITC) 2005, Nov 8-10, Austin, TX, pp. 1038-1047. In this paper, we utilize multi-level Compatible Observability Don’t Cares (CODCs) which are computed during the logic synthesis phase of a design, to speed up SAT based ATPG. Our approach is about 30% faster than a commercial ATPG tool (with no aborted faults, whereas the commercial tool has several aborts). Presentation slides.
  • “SAT-based ATPG using Multi-level Compatible Don’t-Cares”, Saluja, Gulati, Khatri. ACM Transactions on Design Automation of Electronic Systems (TODAES), vol. 13, number 2, April 2008, pp. 24:1-24:18. In this paper, we present a Don’t Care enhanced SAT based ATPG engine, which outperforms a commercial ATPG tool. Our paper utilizes approximate CODCs to speed up both the fault excitation and fault propagation steps of ATPG, achieving significant speedup over a commercial ATPG tool.
  • “Towards Acceleration of Fault Simulation using Graphics Processing Units”, Gulati, Khatri. ACM/ EDAC/IEEE Design Automation Conference (DAC) 2008, June 8-13 2008, Anaheim, CA, pp. 822-827. We demonstrated a 35X speedup (estimated 240X speedup with a 8-GPU server) for fault simulation, over a leading commercial tool. This was the first published paper on the use of GPUs for CAD algorithm acceleration. This paper is also listed in the “GPUs for VLSI CAD” section. Presentation slides.
  • “Fault Table Computation on GPUs”, Gulati, Khatri. Journal of Electronic Testing: Theory and Applications (JETTA). Vol 26, number 2, April 2010. pp 195-209. In this paper, we utilize the GPU to perform fault table generation, with a speedup of 20X (projected 80X speedup with a 8-GPU server) compared to a CPU based implementation. This paper is also listed in the “GPUs for VLSI CAD” section. This paper also appeared in the International Test Synthesis Workshop (ITSW) 2009, where it received the Best student paper award.
  • Invited Paper “A PTL based Highly Testable Structured ASIC Design Approach”, Gulati, Jayakumar, Khatri. International Symposium on Integrated Circuits (ISIC) 2009, Singapore. December 14-16, 2009.
  • “A Modified Scan-D Flip-flop Design to Reduce Test Power”, Ganesan, Khatri. 15th IEEE/TTTC International Test Synthesis Workshop (ITSW) 2008, April 7-9, Santa Barbara, CA. This paper presents the design of a scan flip-flop which reduces circuit power (by 14%) during the scan shift operations. Presentation slides.
  • “A Robust Pulse-triggered Flip-Flop based Enhanced Scan Cell Design”, Kumar, Bollapalli, Garg, Soni, Khatri. IEEE International Conference on Computer Design (ICCD) 2009, Lake Tahoe, CA. October 4-7, 2009. In this paper, we present a robust pulsed flip-flop design, and demonstrate its use in an enhanced scan flip-flop. Our pulsed flip-flop based enhanced scan cell has a 14% better delay than a traditional D flip-flop based enhanced scan cell. Presentation slides.
  • “An Efficient Pulse Flip-Flop Based Launch-on-Shift Scan Cell”, Kumar, Bollapalli, Khatri. IEEE International Symposium on Circuits and Systems (ISCAS) 2010, Paris, France. May 30 – Jun 2, 2010. This paper reports on a launch-on-shift scan flip-flop, implemented using a pulsed latch. Our design is faster, smaller and less power hungry (by upwards of 20%) than the existing method of designing such a scan cell.
  • “The Top of Testing’s Most Wanted List – What is the most critical Testing challenge? (or have all the bad guys been caught already?)”, invited panelist along with some leading researchers in VLSI testing. This panel was part of the International Test Synthesis Workshop (ITSW) 2007, San Antonio, TX, March 5-7, 2007.
  • “Are we Fighting a Losing Battle, Dealing with Numerous and Complex Defects?”, invited to serve as a panelist along with 3 leaders in the field. Peer panelists were Dr. Tom Williams (Synopsys), Prof. Melvin Bruer (USC), and Al Crouch (Inovys Corporation). The panel was part of the International Test Synthesis Workshop (ITSW) 2006, Santa Barbara, CA, April 9-12, 2006.