ECEN 6009 — Research Topics in VLSI
Instructor Sunil P Khatri Office: ECOT432 Phone/Fax: 5-1962 E-mail: firstname.lastname@example.org Class time : M 6:00pm - 830pm Office Hours: By appointment
- Course Objective
- Course Outline
- Software Tools
- Grading Policy
- Papers to be Covered
- Project related material
The course will cover several new research topics relating to VLSI. The broad areas of these topics will be embedded systems scheduling, nano-electronics and quantum computing. The goals of this course are:
- To cover important papers in the above areas in detail, and become intimately familiar with the current state of research in these areas.
- To come up with new research topics and directions in the above areas, which should naturally occur as a result of the above exercise.
- Each student will select one of the new research topics which we come up with, and do a class project on this topic. There will be no final exam.
Graduate standing, with some previous course or practical experience in VLSI. If you dont meet the requisites and are still very interested in the class, please see me. A typical EE Bachelors degree would usually meet these requirements.
The course will cover readings in the following research areas:
- Embedded Systems Scheduling
- Quantum computing
The class project may involve hands-on use of SPICE (a circuit simulator), SPACE-3D (a 3-D parasitic extractor), SIS (a logic synthesis tool), OCTAVE (a Mathematica style tool) and VIS (a formal verification tool). Class projects may involve programming in C or PERL.
SPICE can be run on Linux systems, and SPACE-3D on Linux/Solaris/HP systems. SIS and VIS can be run on Linux systems and so can OCTAVE. You may also find that writing PERL scripts may enable you to be productive while writing your software for class projects or homework assignments.
Students will be given accounts on machines in CU where these tools are installed. Additionally, if students want to install these tools on their own machines at home, they should see me. Most of these tools are NOT ported to Windows systems, and I will not be able to help if you plan to install these tools on such systems.
The class will cover research papers, and will not have a textbook.
- 10% Class participation and involvement.
- 20% 1 Mid-term exam.
- 20% 1-2 Paper presentations
- 50% Research-oriented class project in lieu of final exam. The class project is one of the most important parts of this class. It will enable you to dive deeper into a particular topic from the class.
Mid-term exams will be open notes, open book etc.
If you have a class project in mind then please let me know. I will determine if the project is sufficiently interesting from a research standpoint, and we will discuss project deliverables together. Alternately, you can choose your project from a list of projects which I will distribute to the class about 45 days (or earlier) before the end of the semester.
“Scheduling ALgorithms for Multiprogramming in a Hard Real-time Environment”, Liu and Layland in pdf format.
“Scheduling Periodically Occurring Tasks on Multiple Processors”, Lawler and Martel in pdf format.
“Low Power System Scheduling and Synthesis”, Jha in pdf format.
“Energy Efficient Fixed-Priority Scheduling for Real-time Systems on Variable Voltage Processors”, Quan and Hu in pdf format.
“Battery-aware Static Scheduling for Distributed Real-time Embedded Systems”, Luo and Jha in pdf format.
“Power-conscious Scheduling of Periodic Task Graphs and Aperiodic Tasks in Distributed Real-time Embedded Systems”, Luo and Jha in pdf format.
“A DVS algorithm for Dynamic-Priority Hard Real-time Systems using Slack Time Analysis “, Kim, Kim and Min in pdf format.
“Performance Estimation of Embedded Software with Instruction Cache Modeling”, Li, Malik and Wolfe in pdf format.
“A transformation based algorithm for reversible logic synthesis”, Miller, Maslov and Dueck in pdf format.
“Smaller two-qubit circuits for quantum communication and computation”, Shende, Markov and Bullock in pdf format.
“Synthesis and optimization of Threshold logic networks with application to nanotechnologies”, Zhang, Gupta, Zhong and Jha in pdf format.
“Carbon Nanotube interconnects – a process solution”, Li, Ye, Koehne, Ng, Han, Meyyappan in pdf format.
“Carbon Nanotube field-effect transistors and logic circuits”, Martel, Derycke, Appenzeller, Wind, Avourins in pdf format.
Additional papers to be added soon
Sunil P Khatri / University of Colorado at Boulder / email@example.com