The Computer Engineering and Systems Group (CESG) Department of Electrical and Computer Engineering

EE 449/749 — Microprocessor System Design.

Fall 2023

Instructor:

Sunil P Khatri, email:i r t a h k l i n u s (spell backwards, drop spaces) at tamu dot edu
Phone: 979-845-8371
Office: Wisenbaker 333F
Syllabus: click here

Class Hours:

Mon/Wed 6:20 pm – 7:15 pm in ZACH 444.

Lab Hours:

Section 200/501/601: Thu, 8:00 am – 9:50 am, ZACH 333
Section 502/602: Thu, 10:10 am – 12:00 pm, ZACH 333
Section 503/603: Thu, 12:15 pm – 2:05 pm, ZACH 333
Section 504/604: Fri, 8:00 am – 9:50 pm, ZACH 333
Section 505/605: Fri, 10:20 am – 12:10 pm, ZACH 333
Section 506/606: Fri, 12:40 [m – 2:30 pm, ZACH 333
Section 700 (asynchronous class, asynchronous labs <discuss demo and report turn-in schedule with your TA>)

Office hours:

Wednesday 5:00 pm – 6:15 pm in WEB 333F

TA Information:

    1. Name: Shah-Wei Chu
      Sections: 449 (504, 505, 506) and 749 (604, 605, 606) and 749-700 (labs 1-3)
      Zoom: https://tamu.zoom.us/j/4897334510
      E-mail: shaowei22@tamu.edu
      Office Hours: Thursday 9am – 11am, WEB 321 (or by appointment)
    2. Name: Vinay Bayaneni
      Sections: 449 (501, 502, 503) and 749 (601, 602, 603) and 749-700 (labs 4-7)
      Zoom: https://tamu.zoom.us/j/92462605690
      E-mail: vinaybayaneni@tamu.edu
      Office Hours: Tuesday 10am – 12noon in ZACH 332.

Class Conscience:

Resources:

Class notes:

    • Posted here on this web page. The notes are either developed by the course instructor or derived from other original copyrighted classnotes.

 Grading Policy

    • Homeworks 20%.
      • I will assign homework assignments on Wednesday, and you will have one week to turn in your solution via canvas. 50% credit will be given for homework that is late by up to one week. Zero credit will be given for homework that is late by more than one week.
      • Upload your homework solution to canvas as instructed.
      • DO NOT upload a zip file for the entire homework assignment!
      • You will have only ONE attempt to upload your homework solution.
      • For full credit, you should include comments in any code (Verilog or C) that you use for your answer.
    • Lab 21%
      • The lab grade will be equally divided among the number of lab sessions.
      • Lab reports must be turned in individually. Lab reports for Lab i should be turned in by the end of the day (11:59 pm) of the first session of Lab i+1. Demos for Lab i are allowed until the end of the first session of Lab i+1.
      • 50% credit will be given for reports that are late by a week. 0% credit will be given for reports that are late by more than a week.
      • For full credit, you should include comments in any code (Verilog or C) that you include in the lab report.
    • Two tests 55%
      • Test1 (2 hours) 27.5%, Test2 (2 hours) 27.5%. Both tests will be open notes, and may have lab related questions. Test2 will be cumulative.
      • TEST 1: Wed 10/11, 7:30 pm – 9:30 pm. Location TBD
      • TEST 2: Thu 12/7, 7:30 am – 9:30 am. Location ZACH 444
      • Extended office hours will be held before each test. The times for these office hours will be announced closer to the time of the test.
    • Class attendance 4%
      • You will receive 1% credit for each question you ask in class quizzes, up to a maximum of 4%. For ECEN 749 section 700, you will get these points for free.
    •  There will be a separate curve for ECEN 449 and ECEN 749. ECEN 749 students will have extra questions on the homework assignments, as well as the exam.

Course Objective:

      • The goal of this course is to provide the student with an in-depth knowledge of digital circuit design using an embedded platform as an implementation method. We will cover hardware and software co-design, using a commercial FPGA with an embedded on-chip microprocessor.
      • At the end of the course the student should be able to view the design of digital systems from a embedded hardware/software perspective and obtain a set of fundamental concepts and design skills that can be applied to a wide variety of digital design problems.

Important Logistical Issues:

      • As indicated in the first week of class, you are responsible to read this page and familiarize yourself with the important logistical information on it.
      • *Excused absences:* Rules concerning excused absences may be found at http://student-rules.tamu.edu/rule7.htm. In particular, except for absences due to religious obligations, the student must notify his or her instructor in writing (acknowledged e-mail message is acceptable) prior to the date of absence if such notification is feasible. In cases where advance notification is not feasible (e.g., accident, or emergency) the student must provide notification by the end of the second working day after the absence. This notification should include an explanation of why notice could not be sent prior to the class. If the absence is excused, the instructor must either provide the student with an opportunity to make up any quiz, exam or other graded activities or provide a satisfactory alternative to be completed within 30 calendar days from the last day of the absence.
      • *Days of religious observance:* By state law, if a student misses class due to an obligation of his or her religion, the absence is excused. A list of days of religious obligation for the coming semester may be found at http://dof.tamu.edu/faculty/policies/religiousobservance.php.
      • *Disruptive behavior:* If a student’s behavior in class is sufficiently disruptive to warrant immediate action, the instructor is entitled to remove a student on an interim basis, pending an informal hearing with the Head of the Department offering the course. This hearing must take place within three working days of the student’s removal. This rule and supporting information may be found at http://studentrules.tamu.edu/rule21.htm.
      • *Accommodations for students with disabilities:* It is the responsibility of the student to provide instructors with documentation showing they have registered with Disability Services and requested accommodation. Instructors then have the responsibility to work with Disability Services to provide reasonable accommodations. If a student who has not registered with Disability Services requests an accommodation, they should be referred to Disability Services at http://disability.tamu.edu .
      • *Email Policy:* Please remember that your official TAMU email will be used as an official means of communicating class information to you.
      • *Academic Honesty:* Remember that plagiarism will not be tolerated and will be dealt with under the Aggie Honor System Office guidelines. Upon discovering a suspected violation of the Aggie Honor code, I will contact the Aggie Honor System office http://www.tamu.edu/aggiehonor/.
Tentative Schedule – subject to change
Week Monday Lecture Wednesday Lecture Laboratory Comments
1 (8/21, 8/23) Class overview Verilog No Lab this week!!!  

Lab Policy

 
2 (8/28, 8/30) Verilog Verilog Lab 1 – Vivado Un-homework on C

 Un-homework on Verilog (with solution)
3 (9/04, 9/06) LABOR DAY Verilog Lab 2 – SDK HW1 out 9/06, due 9/13
4 (9/11, 9/13) Verilog C Programming Continue with Lab 2
5 (9/18, 9/20) C Programming Tips on C Programming Lab 3 – Hardware and Software
6 (9/25, 9/27) Tips on C Programming FPGAs  and Reconfigurable Computing (User Aspects) Continue with Lab 3  

HW2 out 9/27, due 10/04
7 (10/02, 10/04) FPGAs and reconfigurable computing (User aspects) FPGAs and reconfigurable computing (User aspects) Lab 4 – Booting Linux on the Zybo board
8 (10/09, 10/11) FALL BREAK Linux Introduction Lab 5 – Simple Kernel Module Sample Exam and solution

TEST 1 on Wed 10/11, 7:30 pm – 9:30 pm
9 (10/16, 10/18) Linux introduction Linux introduction
10 (10/23, 10/25) Linux Introduction Pulse Modulation Continue with Lab 5
11

(10/30, 11/01)

 Pulse Modulation Pulse Modulation Lab 6 – Device Drivers HW3 out 11/01, due 11/08
12

(11/06, 11/08)

 Hardware-software Communication Hardware-software communication Continue with Lab 6
13

(11/13, 11/15)

 FPGAs  and Reconfigurable Computing (Under the hood) FPGAs and Reconfigurable Computing (under the hood) Lab 7 – Built-in kernel modules Q-drop deadline 11/15/23 at 5;00 pm

HW4 out 11/13, due 11/20
14

(11/20, 11/22)

 FPGAs and Reconfigurable Computing (under the hood) READING DAY THANKSGIVING  

 
15

(11/27, 11/29)

 Transmission Lines Transmission Lines Continue with Lab 7
16

(12/04, 12/06)

 Memories NO CLASS No Lab Sample Exam and solution

TEST 2 on Thu 12/07, 7:30 am – 9:30 am