EE 699— VLSI Logic Synthesis
Instructor Sunil P Khatri Office: 333F WERC Phone: 979-845-8371 Fax: 979-845-2630 E-mail: i r t a h k l i n u s (spell backwards, drop spaces) @tamu.edu Class time : MW 4:10p - 5:25p, CHEN 111 Office Hours: MW 3:00p - 4:00p or by appointment Text: None, course will be taught from lecture notes which are posted on this page.
- Course Objective
- Course Prerequisites
- Course Outline
- Important Logistical Issues
- Homework, Exams and Grading
- Class Notes
- Homework and other Postings
- Software Resources
The goal of this course is to provide the student with a detailed knowledge of different methods for logic representation, manipulation, and optimization, for both combinational and sequential logic. The course views logic synthesis in the context of the implementation styles that are popularly used in industry today. At the end of the course the student should be able to perform the design of digital systems from a sound theoretical and practical perspective and have access to and an understanding of a suite of powerful tools that can be applied to a wide variety of CAD for VLSI problems. With this course, the student will obtain a thorough understanding of the state of the art for VLSI logic synthesis in academia and in industrial practice. Additionally, through the course project, an in-depth understanding and appreciation of a particular topic in logic synthesis will be obtained.
The intended audience would be graduate students interested in the algorithms and techniques used in contemporary VLSI logic synthesis. The course could serve as a starting point for possible research in this area.
Graduate standing, or instructor consent.
0. Implementation of Logic (or What Drives Logic Synthesis?) Brief introduction to MOS transistor fundamentals PLAs Static CMOS logic gates Other CMOS logic gates 1.Introduction introduction-I (logic functions and their representation) introduction-II (unate functions/recursive paradigm, Quine McCluskey) 2.Two Level Minimization ESPRESSO two level minimization multivalued minimization BDD's 3.Multi-Level Logic Synthesis introduction (Boolean networks, factored forms) division simplification full simplify SPFDs technology mapping timing optimization application to special logic implementation styles 4.Logic Synthesis for Quantum Computers introduction quantum technology mapping quantum don't cares 5.Sequential Logic Synthesis introduction (FSM networks) node minimization state minimization retiming and resynthesis verification state assignment
As I indicated in the first lecture, you are responsible to read this page and familiarize yourself with the important logistical information on it.
Please remember that email will be used as an official means of communicating class information to you. You should make sure that the email address that you gave me on the first day of class is a current and functioning address. In case of any changes in your email address, please let me know ASAP.
Per University Regulations, I will allow a student who is absent from class for the observance of a religious holy day to take an examination or complete an assignment scheduled for that day within a reasonable time after the absence, if, not later than the 15th day after the first day of the semester, the student notifies me that they would be absent on which particular days.
If you believe that you have a disability requiring an accomodation, the University provides academic adjustments and auxiliary aids as defined under the law. In such a case, you should register your documentation with the Office of Services for Students with Disabilities before any accomodations are made. Once this office reviews your documentation and verifies your condition, I will make reasonable accomodations.
Remember that plagiarism will not be tolerated and will be dealt with under the Aggie Honor System Office guidelines.
20% 5-7 Homework assignments 30% One midterm exam 50% Class project (in lieu of Final Exam)
In general you will have one week to do a homework assignment. The due date for each homework will be indicated. A homework turned in one week late will be penalized 50%. A homework turned in later than a week will receive no credit. You are welcome to work together on homework, but you should not turn in identical solutions, or one solution for multiple students.
There will be one open notes, open book, midterm exam.
There will be a class project in lieu of final exam. The project will involve research and implementation. A list of candidate projects will be circulated about 60 days before the end of the course. Students may choose to do a project not on this list, after consulting with the instructor. In prior offerings of this course, several such class projects have resulted in technical publications at leading conferences. The topic areas of these projects will broadly cover VLSI design and CAD, and not be restricted to VLSI logic synthesis alone. There will be no penalty for negative results in the project, as long as all theoretical and implementation options are thoroughly explored by the student.
I will grade EE699 on a curve. Our class conscience is : Surya Prakash (firstname.lastname@example.org)
Frequently used symbols. I created this for an undergraduate course in logic, but you may find it useful as well.
Homework assignments and solutions:
The logic synthesis system SIS and the logic minimization program ESPRESSO are part of the homework problems and the subject of some of the lectures. The student will be given computer accounts on EE machines where the programs are installed. Alternately the programs can be downloaded and installed on the student on their own machines. If you wish to download and install the software on your machine, please let me know.
The links below are for the circuit projects..
Sunil P Khatri / Texas A&M University /